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| Intel Corporation - IA-32 IntelR Architecture Software Developer's Manual Volume 3: System Programming Guide |
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| Предметный указатель |
16-bit code, mixing with 32-bit code 17-1
32-bit code, mixing with 16-bit code 17-1
32-bit physical addressing, description of 3-20
32-bit physical addressing, overview 3-6
36-bit physical addressing, overview 3-6
36-bit physical addressing, using PSE-36 paging mechanism 3-34
36-bit physical addressing, using the PAE paging mechanism 3-28
8086 emulation, support for 16-1
8086 processor, exceptions and interrupts 16-8
8086/8088 processor 18-6
8087 math coprocessor 18-7
82489DX 18-27 18-28
82489DX relationship with local and I/O APICs 8-5
A (accessed) flag, page-table entries 3-26
A20M# signal 16-3 18-37
Aborts, description of 5-6
Aborts, restarting a program or task after 5-7
AC (alignment check) flag, EFLAGS register 2-9 5-49 18-6
Access rights, checking 2-21
Access rights, checking caller privileges 4-29
Access rights, description of 4-27
Access rights, invalid values 18-23
ADC instruction 7-5
Add instruction 7-5
Address space, of task 6-18
Address translation in real-address mode 16-3
Address translation logical to linear 3-7
Address translation overview 3-6
Address translation, 2-MByte pages, using 36-bit physical addressing 3-30
Address translation, 4-KByte pages, using 32-bit physical addressing 3-20
Address translation, 4-KByte pages, using 36-bit physical addressing 3-29
Address translation, 4-MByte pages, using 32-bit physical addressing 3-21
Address translation, 4-MByte pages, using 36-bit physical addressing 3-34
Address, size prefix 17-2
Addressing, segments 1-8
Advanced programmable interrupt controller see "I/O APIC" "Loal
Alignment check exception (#AC) 2-9 5-49 5-50 18-13 18-25
Alignment, alignment check exception 5-49 5-50
Alignment, checking 4-31
Alignment, exception 18-13
AM (alignment mask) flag, CR0 control register 2-9 2-13 18-22
AND instruction 7-5
APIC see "I/O APIC" "Loal
APIC bus, arbitration mechanism and protocol 8-31 8-39
APIC bus, bus message format 8-40 F-1
APIC bus, diagram of 8-3 8-4
APIC bus, EOI message format 8-18 F-1
APIC bus, mesage formats F-1
APIC bus, nonfocused lowest priority message F-3
APIC bus, short message format F-2
APIC bus, SMI message 13-2
APIC bus, status cycles F-4
APIC bus, structure of 8-5
APIC feature flag, CPUID instruction 8-9
APIC global enable flag, IA32_APIC_BASE MSR 8-11
APIC_BASE_MSR 8-11
Arbitration, APIC bus 8-39
ARPL instruction 2-21 4-31
At-retirement, counting 15-44
At-retirement, events 15-26 15-28 15-44 15-53 A-25
Atomic operations, automatic bus locking 7-4
Atomic operations, effects of a locked operation on internal processor caches 7-7
Atomic operations, guaranteed, description of 7-3
Atomic operations, overview of 7-2 7-3 7-4
Atomic operations, software-controlled bus locking 7-4
Auto HALT restart, field, SMM 13-14
Auto HALT restart, SMM 13-14
Automatic bus locking 7-4
B (busy) flag, TSS descriptor 6-7 6-13 6-14 6-17 6-18 7-4
B (default stack size) flag, segment descriptor 17-2 18-35
B0-B3 (breakpoint condition detected) flags, DR6 register 15-4
Backlink see "Previous task link"
Base address fields, segment descriptor 3-11
BD (debug register access detected) flag, DR6 register 15-4 15-9
Binary numbers 1-8
BINIT# signal 2-22
Bit order 1-6
BOUND instruction 2-4 5-5 5-27
BOUND range exceeded exception (#BR) 5-27
BPO#, BP1#, BP2#, and BP3# pins 15-20
Branch record, branch trace message 15-15
Branch record, saving 15-13
Branch record, saving as a branch trace message 15-16
Branch record, structure 15-14
Branch record, structure of in BTS buffer 15-36
Branch trace message see "BTM"
Branch trace store see "BTS"
Breakpoint exception (#BP) 5-5 5-25 15-1 15-10
Breakpoints, breakpoint exception (#BP) 15-1
Breakpoints, data breakpoint 15-6
Breakpoints, data breakpoint exception conditions 15-9
Breakpoints, description of 15-1
Breakpoints, DR0-DR3 debug registers 15-3
Breakpoints, example 15-6
Breakpoints, exception 5-25
Breakpoints, field recognition 15-6
Breakpoints, general-detect exception condition 15-9
Breakpoints, I/O breakpoint exception conditions 15-9
Breakpoints, instruction breakpoint 15-6
Breakpoints, instruction breakpoint exception condition 15-7
Breakpoints, LEN0 - LEN3 (Length) fields, DR7 register 15-6
Breakpoints, R/W0-R/W3 (read/write) fields, DR7 register 15-5
Breakpoints, single-step exception condition 15-10
Breakpoints, task-switch exception condition 15-10
BS (single step) flag, DR6 register 15-4
BSP flag, IA32_APIC_BASE MSR 8-11
BSWAP instruction 18-4
BT (task switch) flag, DR6 register 15-4 15-10
BTC instruction 7-4
BTF (single-step on branches) flag, DebugCtlMSR MSR 15-15 15-20
BTMs (branch trace messages), description of 15-15
BTMs (branch trace messages), enabling 15-13 15-18
BTMs (branch trace messages), TR (trace message enable) flag, IA32_DEBUGCTL MSR 15-13
BTR instruction 7-4
BTS (branch trace store) facilities, availability of 15-11
BTS (branch trace store) facilities, BTS_UNAVAILABLE flag, IA32_MISC_ENABLE MSR 15-34 B-8
BTS (branch trace store) facilities, detection of 15-16
BTS (branch trace store) facilities, introduction to 15-11
BTS (branch trace store) facilities, setting up BTS buffer 15-18
BTS (branch trace store) facilities, writing an interrupt service routine for 15-18
BTS buffer, description of 15-34
BTS buffer, introduction to 15-11 15-16
BTS buffer, records in 15-36
BTS buffer, setting up 15-18
BTS buffer, structure of 15-35
BTS instruction 7-4
BTS_UNAVAILABLE flag, IA32_MISC_ENABLE MSR 15-34 B-8
Built-in self-test (BIST), description of 9-1
Built-in self-test (BIST), performing 9-2
Bus errors, detected with machine-check architecture 14-14
Bus hold 18-39
Bus locking 7-3 18-38
byte order 1-6
C (conforming) flag, segment descriptor 4-14
C1 flag, x87 FPU status word 18-8 18-17
C2 flag, x87 FPU status word 18-9
Cache control 10-22
Cache control, cache management instructions 10-18
Cache control, cache mechanisms in IA-32 processors 18-31
Cache control, caching terminology 10-4
Cache control, CD flag, CR0 control register 10-10 18-23
Cache control, choosing a memory type 10-8
Cache control, flags and fields 10-10
Cache control, flushing TLBs 10-21
Cache control, G (global) flag, page-directory entries 10-13 10-21
Cache control, G (global) flag, page-table entries 10-13 10-21
Cache control, internal caches 10-1
Cache control, MemTypeGet() function 10-32
Cache control, MemTypeSet() function 10-34
Cache control, MESI protocol 10-4 10-9
| Cache control, methods of caching available 10-5
Cache control, MTRR initialization 10-31
Cache control, MTRR precedences 10-31
Cache control, MTRRs, description of 10-22
Cache control, multiple-processor considerations 10-35
Cache control, NW flag, CR0 control register 10-13 18-23
Cache control, operating modes 10-12
Cache control, overview of 10-1
Cache control, page attribute table (PAT) 10-37
Cache control, PCD flag, CR3 control register 10-13
Cache control, PCD flag, page-directory entries 10-13 10-14 10-37
Cache control, PCD flag, page-table entries 10-13 10-14 10-37
Cache control, PGE (page global enable) flag, CR4 control register 10-13
Cache control, precedence of controls 10-14
Cache control, preventing caching 10-17
Cache control, protocol 10-9
Cache control, PWT flag, CR3 control register 10-13
Cache control, PWT flag, page-directory entries 10-13 10-37
Cache control, PWT flag, page-table entries 10-13 10-37
Cache control, remapping memory types 10-31
Cache control, setting up memory ranges with MTRRs 10-25
Cache control, variable-range MTRRs 10-27
Caches 2-6
Caches, cache hit 10-4
Caches, cache line 10-4
Caches, cache line fill 10-4
Caches, cache write hit 10-4
Caches, description of 10-1
Caches, effects of a locked operation on internal processor caches 7-7
Caches, enabling 9-8
Caches, management, instructions 2-21 10-18
Caching, cache control protocol 10-9
Caching, cache line 10-4
Caching, cache management instructions 10-18
Caching, cache mechanisms in IA-32 processors 18-31
Caching, caching terminology 10-4
Caching, choosing a memory type 10-8
Caching, flushing TLBs 10-21
Caching, implicit caching 10-20
Caching, internal caches 10-1
Caching, L1 (level 1) cache 10-3
Caching, L2 (level 2) cache 10-3
Caching, L3 (level 3) cache 10-3
Caching, methods of caching available 10-5
Caching, MTRRs, description of 10-22
Caching, operating modes 10-12
Caching, overview of 10-1
Caching, self-modifying code, effect on 10-19 18-32
Caching, snooping 10-4
Caching, store buffer 10-22
Caching, TLBs 10-3
Caching, UC (strong uncacheable) memory type 10-5
Caching, UC- (uncacheable) memory type 10-5
Caching, WB (write back) memory type 10-6
Caching, WC (write combining) memory type 10-6
Caching, WP (write protected) memory type 10-6
Caching, write-back caching 10-5
Caching, WT (write through) memory type 10-6
Call gates, 16-bit, interlevel return from 18-35
Call gates, accessing a code segment through 4-18
Call gates, description of 4-17
Call gates, for 16-bit and 32-bit code modules 17-2
Call gates, introduction to 2-3
Call gates, mechanism 4-19
Call gates, privilege level checking rules 4-20
Call instruction 2-4 3-9 4-12 4-13 4-18 4-24 6-3 6-12 6-13 17-7
Caller access privileges, checking 4-29
Calls between 16- and 32-bit code segments 17-4
Calls, controlling the operand-size attribute for a call 17-7
Calls, returning from 4-24
Catastrophic shutdown detector 13-19
CC0 and CC1 (counter control) fields, CESR MSR (Pentium processor) 15-63
CD (cache disable) flag, CR0 control register 2-13 9-8 10-10 10-12 10-14 10-17 10-35 10-36 18-22 18-23 18-31
CESR (control and event select) MSR (Pentium processor) 15-62 15-63
CLFLSH feature flag, CPUID instruction 9-9
CLFLUSH instruction 2-14 7-8 9-9 10-19
CLI instruction 5-9
Clocks, counting processor clocks 15-49
CLTS instruction 2-20 4-26
Cluster model, local APIC 8-29
CMOVcc instructions 18-4
CMPXCHG instruction 7-4 18-4
CMPXCHG8B instruction 7-4 18-4
Code modules, 16 bit vs. 32 bit 17-2
Code modules, mixing 16-bit and 32-bit code 17-1
Code modules, sharing data among mixed-size code segments 17-3
Code modules, transferring control among mixed-size code segments 17-4
Code segments, accessing data in 4-12
Code segments, accessing through a call gate 4-18
Code segments, description of 3-13
Code segments, descriptor format 4-3
Code segments, descriptor layout 4-3
Code segments, direct calls or jumps to 4-13
Code segments, executable (defined) 3-11
Code segments, paging of 2-5
Code segments, pointer size 17-5
Code segments, privilege level checking when transferring program control between code segments 4-12
Code segments, size 3-11
Compatibility, IA-32 architecture 18-1
Compatibility, software 1-6
Condition code flags, x87 FPU status word compatibility information 18-8
Conforming code segments, accessing 4-15
Conforming code segments, C (conforming) flag 4-14
Conforming code segments, description of 3-14
Context, task see "Task state"
Control registers, CR0 2-12
Control registers, CR1 (reserved) 2-12
Control registers, CR2 2-12
Control registers, CR3 (PDBR) 2-5 2-12
Control registers, CR4 2-12
Control registers, description of 2-12
Control registers, introduction to 2-5
Control registers, qualification of flags with CPUID instruction 2-18
Coprocessor segment overrun exception 5-34 18-13
Counter mask field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-60
CPL, description of 4-8
CPL, field, CS segment selector 4-3
CPUID instruction 7-14 15-22 15-61 18-2 18-4 18-39
CPUID instruction, qualification of CR4 control register flags 2-18
CR0 control register 18-7
CR0 control register, description of 2-12
CR0 control register, introduction to 2-5
CR0 control register, state following processor reset 9-2
CR1 control register (reserved) 2-12
CR2 control register, description of 2-12
CR2 control register, introduction to 2-5
CR3 control register (PDBR), associated with a task 6-1 6-3
CR3 control register (PDBR), changing to access full extended physical address space 3-31
CR3 control register (PDBR), description of 2-12 3-23
CR3 control register (PDBR), format with physical address extension enabled 3-29
CR3 control register (PDBR), in TSS 6-5 6-18
CR3 control register (PDBR), introduction to 2-5
CR3 control register (PDBR), invalidation of non-global TLBs 3-37
CR3 control register (PDBR), loading during initialization 9-13
CR3 control register (PDBR), memory management 2-5
CR3 control register (PDBR), page directory base address 2-5
CR3 control register (PDBR), page table base address 2-4
CR4 control register, description of 2-12
CR4 control register, enabling control functions 18-2
CR4 control register, inclusion in IA-32 architecture 18-21
CR4 control register, introduction to 2-5
CS register 18-12
CS register, saving on call to exception or interrupt handler 5-15
CS register, state following initialization 9-6
CTR0 and CTR1 (performance counters) MSRs (Pentium processor) 15-62 15-65
Current privilege level see "CPL"
D (default operation size) flag, segment descriptor 17-2 18-35
D (dirty) flag, page-table entries 3-26
D/B (default operation size/default stack pointer size and/or upper bound) flag, segment descriptor 3-11 4-5
Data breakpoint exception conditions 15-9
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