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Äàòà èçìåíåíèÿ: Wed Nov 19 22:32:38 2014
Äàòà èíäåêñèðîâàíèÿ: Sat Apr 9 22:53:32 2016
Êîäèðîâêà:


ARM
. .. , .-., , ..-.. .., ..

12:



· ARM

2


ARM Powered Products

3



ARM ·

4



· ARM 32- . · ARM :
­ Byte - 8 bits ­ Halfword - 16 bits ( ) ­ Word - 32 bits ( )

· ARM
­ 32-bit ARM Instruction Set ­ 16-bit Thumb Instruction Set

5



· ARM:
­ User : , ­ FIQ : , high priority (fast) ­ IRQ : , low priority (normal)

­ Supervisor : Software Interrupt instruction
­ Abort : ­ Undef : ­ System : , 6 User


ARM
Current Visible Registers
Abo Und rtMod SVCMode IRQ ef Mode FIQ Mode e User Mode
r0

r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc)
cpsr spsr

Banked out Registers
User
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQ
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

IRQ

SVC

Undef

Abort

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

spsr

7



User
r0 r1 r2

FIQ

IRQ

SVC

Undef

Abort

r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr

User mode r0-r7, r15, and cpsr

r8 r9

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

Thumb Low registers

r10 r11 r12 r13 (sp) r14 (lr)

Thumb High registers
r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

spsr

Note: System mode , User mode
8



· ARM 37 32-bits.
­ ­ ­ ­ 1 : program counter 1 : current program status 5 program status 30

· :
­ ­ ­ ­ r0-r12 r13 (the stack pointer, sp) r14 (the link register, lr) program counter, r15 (pc) current program status register, cpsr

(except System) spsr (saved program status register)

9



31 28 27 24 23 16 15 8 7

NZCVQ J f
·
­ ­ ­ ­ N Z C V = = = =

Undefined s x
·

IFT mode c
6 5 4

0


Negative Zero Carried out oVerflowed

.
­ I = 1: IRQ. ­ F = 1: FIQ.

·

T Bit
­ xT ­ T = 0: ARM ­ T = 1: Thumb

·

Sticky Overflow - Q flag
­ 5TE/J ­

·

J bit
­ 5TEJ ­ J = 1: Jazelle

·

Mode bits
­

10


Program Counter (r15)
· ARM:
­ 32 ­ (word aligned)

·

Thumb:
­ 16 ­ (halfword aligned)

·

Jazelle:
­ 8 ­ 4

11



· :
­ CPSR SPSR_ ­ CPSR

0x1C 0x18 0x14 ­ Stores the return address in LR_ 0x10 0x0C ­ Sets PC to vector address 0x08 · : 0x ­ CPSR SPSR_ 04 0x00 ­ PC LR_
· ARM · exception mode · (if appropriate) ARM.

FIQ IRQ (Reserved) Data Abort

Prefetch Abort
Software Interrupt Undefined Instruction

Reset

Vector Table
Vector table 0xFFFF0000 ARM720T ARM9/10 12


ARM
1 Halfword signed halfword / System mode 4 Improved ARM/Thumb Interworking CLZ SA-110 SA-1110 Saturated maths
5TE

Jazelle

Java bytecode ARM9EJ-S
ARM7EJ-S

5TEJ

ARM926EJ-S
ARM1026EJ-S

2

DSP multiplyaccumulate instructions
ARM1020E XScale

3 Thumb instruction ARM set ARM7TDMI 4T

SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support

6

ARM9TDMI

ARM9E-S

ARM720T

ARM940T

ARM966E-S

ARM1136EJ-S

13



ARM ·

14



· ARM .

­

CMP r3,#0 BEQ skip ADD r0,r1,r2 skip

CMP r3,#0 ADDNE r0,r1,r2

·

, , "S". CMP "S".
loop ... SUBS r1,r1,#1 BNE loop

r1 Z ,

15



· :
EQ Equal NE Not equal CS/HS Unsigned higher or same CC/LO Unsigned lower MI Minus PL Positive or Zero VS Overflow VC No overflow HI Unsigned higher LS Unsigned lower or same GE Greater or equal LT Less than GT Greater than LE Less than or equal AL Always Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V 16



·
if (a==0) func(1);

CMP MOVEQ BLEQ

r0,#0 r0,#1 func

· ,
if (a==0) x=0; if (a>0) x=1;

CMP MOVEQ MOVGT

r0,#0 r1,#0 r1,#1

·
if (a==4 || a==10) x=0;

CMP CMPNE MOVEQ

r0,#4 r0,#10 r1,#0

17



· · Branch : Branch :
31 28 27 25 24 23

B{} label BL{} subroutine_label
0

Cond

101L

Offset

Link bit

0 = Branch 1 = Branch with link

Condition field

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· :
­ ­ ­ ­ : ADD : AND : CMP :
ADC
ORR CMN MOV

SUB
EOR TST MVN

SBC
BIC TEQ

RSB

RSC

· ·

, . :
{}{S} Rd, Rn, Operand2

· · Rn

·

barrel shifter.
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Barrel Shifter
LSL : Logical Left Shift ASR: Arithmetic Right Shift
CF

Destination

0

Destination

CF

2
LSR : Logical Shift Right

2,
ROR: Rotate Right

...0

Destination

CF

Destination

CF

2

LSB MSB
RRX: Rotate Right Extended

Destination

CF

CF MSB
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Barrel Shifter:
1
2

Barrel Shifter




21



· :
­ ­ ­ ­ MUL{}{S} Rd, Rm, Rs MLA{}{S} Rd,Rm,Rs,Rn [U|S]MULL{}{S} RdLo, RdHi, Rm, Rs [U|S]MLAL{}{S} RdLo, RdHi, Rm, Rs Rd = Rm * Rs Rd = (Rm * Rs) + Rn RdHi,RdLo := Rm*Rs RdHi,RdLo := (Rm*Rs)+RdHi,RdLo

·


­ MUL
· 2-5 ARM7TDMI · 1-3 StrongARM/XScale · 2 ARM9E/ARM102xE

­ +1 ARM9TDMI (over ARM7TDMI) ­ +1 "long"

22



LDR STR LDRB LDRH LDRSB LDRSH Word STRB STRH

Byte Halfword Signed byte load Signed halfword load

· · :
­ LDR{}{} Rd,
­ STR{}{} Rd,

e.g. LDREQB
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· LDR/STR · ,
­ 0 - 4095 bytes
LDR r0,[r1,#8]

· , :
­ 0-255 bytes. ­

24


· : Offset
r0,[r1,#12]
r1 0x200 12 Base Register

?
STR
r0

0x20 c
0x20 0

0x5

0x5

Source Register for STR

: STR r0,[r1,#12]!


: STR r0,[r1],#12
Updated Base Register
Original Base Register r1 0x20c r1 0x200 Offset 12

0x20 c 0x20 0
0x5

r0 0x5

Source Register for STR

25


LDM / STM
· :
{}
sing_mode> Rb{!},

· 4 :
LDMIA LDMIB LDMDA LDMDB / / / / STMIA STMIB STMDA STMDB

IA

IB

DA

DB

LDMxx r10, {r0,r1,r4} STMxx r10, {r0,r1,r4}
Base Register (Rb)

r10

r4 r1 r0

r4 r1 r0



r4 r1 r0

r4 r1 r0



26


31

(SWI)
28 27 24 23 0

Cond

1 11 1

SWI number (ignored by processor)



· SWI hardware vector · SWI handler SWI number · SWI , · :
­ SWI{}

27


PSR
IFT NZCVQ J U n d e f i n e d mode c f s x · MRS MSR CPSR / SPSR · :
31 28 27 24 23 16 15 8 7 6 5 4 0

­ ­

MRS{} Rd,

; Rd =

MSR{} ,Rm ; = Rm


­ = CPSR or SPSR ­ [_fields] = any combination of `fsxc'

·
­
MSR{} ,#Immediate

28


ARM
· B