... The APIC ID value that specifies a target processor to receive interrupt delivered in logical destination mode in a local xAPIC. ... The local APIC ID register provides the physical destination mode 8-bit or 32-bit ID for the processor, depending on xAPIC mode or x2APIC mode. ... Local APIC ID Register in x2APIC Mode Each logical processor in the system (including clusters with a communication fabric) must be configured with an unique x2APIC ID to avoid collisions of x2APIC IDs. ... Local x2APIC . ...