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Progress on Silicon-Tungsten Calorimeter for SD David Strom University of Oregon · Design Consideration · Silicon Detectors · Electronics · Some Mechanical Details

M. Breidenbach, D. Freytag, G. Haller,O. Milgrome SLAC

R. Frey, D. Strom UO

V. Radeka BNL

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Primary ECAL Design Requirements

· Excellent separation of 's from charged particles Efficiency > 95% for energy flow · Go o d reconstruction of ±, detection of neutral hadrons

· Reasonable EM energy resolution ( < 15%/ E )

· Reconstruct 's and measure p olarization (separate ,, a1, e's)

· Reconstruct Bhabhas and deconvolve luminosity sp ectra Position resolution 100µm, bias 25µm in endcap

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Secondary ECAL Design Requirements

· Excellent electron identification in jets (tag and b/c quarks)

· Partial reconstruction of b/c hadrons in jets

· Go o d impact resolution for long lived SUSY neutrals 1 cm

· Go o d background immunity ­ Bunchlet identification ­ High granularity

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SiW Design Consideration · Transverse shower size scales with Moli`re radius e (9mm in pure W, 16mm in pure Pb) Minimize gaps b etween layers of absorb er Use a high purity tungsten alloy · Sample b etween 1/2 and 2/3 of X0 (1.75mm to 2.5mm of W) · Allow for detector segmentation at a fraction of the Moli` radius Use 5mm ere pads
American Linear Collider Meeting
Signal in Pad (mips) Signal in Pad (mips)

OPAL - 45 GeV Electron Lateral Shower Profiles
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Data

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Shower at 4 X0
Signal in Pad (mips)
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Pad Number Signal in Pad (mips)

Shower at 4 X0

Pad Number

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Pad Number Shower at 6 X0 Signal in Pad (mips)
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Pad Number Shower at 6 X0 Signal in Pad (mips)

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Pad Number

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Silicon Concept

· Readout each wafer with a single chip · Bump b ond chip to wafer · To first order cost indep endent of pixels /wafer · Hexagonal shap e makes optimal use of Si wafer · Channel count limited by p ower consumption and area of front end chip · May want different pad layout in forward region

Front End Chip

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Silicon Design Details
6 mm

· DC coupled detectors · Two metal layers Could a design with only one work? · Keep Si design as simple as p ossible to reduce cost · Cross talk lo ok small with current electronics design
p+

1 mm 1 mm

n

300 mm

n++

1 mm

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Electronics Design
· Chip area driven by feedback capacitor on charge integrator and 3V supply. Need 2000 MIP ( 8 pC) dynamic range for 500 GeV electrons. 10pF feedback capacitor needed · New design samples integrated ( = 200ns) signal after 1µs for each bunch train Lowers cross talk, little gain variation with bunchlet numb er · Timing at the 10ns level should b e p ossible · Current in input transistor pulsed duty cycle < 10-3 0.1mW/ch · Currently estimating chip area and p ower needed for digital section
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Si Prototyp es

· Rough draft of design completed Waiting for chip area estimate to set grip spacing for bump-b onding
to pixels
6.20 +/! 0.04

to pixels

to pixels 15 traces (maximum) from pixels to a typical bump pad row Each trace 0.006 wide

to pixels

Bump Pad Array detail B Traces to bump pads, typical Unit: mm 9/30/02 R. Frey

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6.20 +/! 0.04


Si Prototyp e prop erties ­ leakage current and noise · Radiation damage to detectors is probably dominated by neutrons, 10 â 1010/cm2

< 10nA /pixel leakage current · Exp ect typical leakage current at start of life < 1nA/pixel · Noise from leakage current at end-of-life for 1µ sampling time (can b e adjusted ) and DC coupling scheme is < 350 electrons

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· Largest source of electronics noise will b e front-end input transistor, noise scales as Cin Cin 1/4 p ower1/4 I · Present design has noise: 20 - 30e/pf For most channels the value of Cinput is dominated by stray capacitance of the trace connecting the pixels to the electronics: Cinput 5.7pF(pixel) + 12pF(trace) + 10pF(amp) 30pF - 1000 electrons noise (c.f. 24,000 from MIP) · Analog p ower consumption will probably b e driven by timing requirements (under investigation)

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· Digital p ower may b e dominated by drivers needed to get data off the chip

Data transmission schemes which minimize dissipation of heat on chip are under consideration

Maximum data rate/ chip are small << 3Mbits/s

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Fitting it all together

Cooling ECAL
· Carto on of p ossible barrel calorimeter configuration · Assume heat flows along tungsten and/or copp er heat sink to co oling water (green) · Longest path for heat flow < 1.4m

Inner Tracker

1.25m

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Layout of Individual calorimeter layers:

Brazed Joints

Rolled Tungsten

~3.5mm

Circuit Board

3.6 Meters 1.1-1.3 Meters Silicon

Layer Assembly

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Critical parameter: minimum space b etween tungsten layers.
Heat path Readout Chip Bump Bonds ~1mm Silicon Wafer
Angle subtended by Moliere radius (mrad) Angle subtended by Moliere radius (deg)

Multi-Layer G-10 Wire Bond

20 18 16 14 12 10 8 6 4

SD, Radius to calorimeter = 1.25m

Config.

Radiation length 3.5mm 3.9mm 5.5mm 6.4mm

Moli`re e Radius 9mm 10mm 14mm 17mm

1.0

100% W 92.5% W +1mm gap +1mmCu

0.5

With copper heat sink

2 0

No copper

0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Gap width (mm)

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Heat flow

Back of the envelop e calculation of change in temp erature: · Thermal Conductivity of W alloy 120W/(K-m) · Thermal Conductivity of Cu 400W/(K-m) Need to reduce heat to b elow 100mW/wafer. Physical mo del test in progress

temperature deg. C

20 18 2.5 mm of W 100mW 16 1.0 mm of Cu 100mW 14 1.0 mm of Cu + 2.5 mm of W at 100mW 12 2.5 mm of W 40mW 10 8 6 4 2 0

0

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120 140 Length (cm)

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Mo del of strip of detectors equivalent to blue region:

21.0 cm 14.0 cm

12.1 cm

10.5 cm

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Conclusion · Design of silicon detectors well underway · Electronics rough draft complete Prototyp es will b e ordered once area needed by the digital design is set · Mechanical conceptual design started 1mm gap b etween layers without a copp er heat sink may b e p ossible Gap size dep ends crucially on p ower consumption

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Near Term Plans · Order Si prototyp es ­ so on · Confirm thermal mo del and explore b est coupling metho d of chips to absorb er · Pro duce prototyp e electronics ­ next year · Simulation, more effort needed here: ­ Optimize sampling for energy resolution ­ Optimize pixel layout ­ Would more granularity help? ­ How sensitive is energy flow to Moli` e raer dius?

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