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Silicon/Tungsten ECal for the SD Detector ­ Status and Progress

R. Frey U. Oregon

UT Arlington, Jan 10, 2003


Outline

· ·

Physics Goals for ECal ú Resolution requirements R&D for the Si/W ECal for SD ú Description ú EGS4 model ú Required simulation studies ú Plans

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ECal Goals
· Photons in Jets ú Id. with high efficiency and measure with reasonable E resolution
· ... in a very busy environment. Demand eff>95% with high purity

·

· · · · ·

Photon shower imaging ú g vertexing (impact param. resolution ~1 cm) ú pº_gg ú Separation from nearby photons, MIPs, h-shower fragments MIP tracking (h± , muons) ú Id. Hadrons which shower in ECal Reconstruction of taus (eg t_rn_p+pºn_g-g-mip) b/c reconstruction ­ include neutrals in MQ estimate e's and Bhabhas ­ easy (readout dynamic range) ú Need to revisit requirement for Lum. spectrum Backgrounds immunity ú Segmentation ú Timing
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SD Si/W Features
· · Moliere radius: 9mm x (~2) Transverse segmentation almost independent of cost within reasonable range (watch thermal load) ú Segmentation < Moliere radius _ no problem ú Readout channels detector pixels/1000 Radiation damage probably non-issue (neutrons?) Timing "easily" possible with resolution of 10-20 ns Dynamic range OK Thermal management: Take advantage of low LC duty cycle Flexible long. sampling: Energy resolution vs Money
What are limiting contributions of calor. to jet resolution?
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· · · · ·


e+e-_jj, 200 GeV; LCDRoot FastMC
· · · Perfect pattern recog. 0.01/sqrt(E) 0.01 (EM) 0.01/sqrt(E) 0.01 (HAD)

_ 0.10/sqrt(Ej)

_ 0.11/sqrt(Mjj)

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EM: 0.12/sqrt(E) 0.01 HAD: 0.50/sqrt(E) 0.02 fi0.18/sqrt(Ej)

EM: 0.20/sqrt(E) 0.01 fi 0.19/sqrt(Ej)

HAD: 0.70/sqrt(E) 0.02 fi worse
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Eg

What is minimum energy required for reconstructing neutrals in jets?

E

h0

Eg > 0.5 GeV fi0.19/sqrt(Ej)

Eg > 1 GeV, Eh0 >1 GeV fi worse

Eg > 2 GeV fi terrible

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SD Si/W
· · 5x5 mm2 pixel fi 50M pixels For each (6 inch) wafer: ú 1000 pixels (approx) ú One readout chip ­ analog and digital · Simple, scalable detector design: ú Minimum of fab. steps ú Use largest available wafers fi Detector cost below $2/cm2 fi Electronics cost even less fi A reasonable (cheap?) cost M. Breidenbach, D. Freytag, G. Haller, M. Huffer, J.J Russell Stanford Linear Accelerator Center R. Frey, D. Strom U. Oregon V. Radeka Brookhaven National Lab

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Putting together a layer

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Wafer and readout chip

Use bump-bonding technique to mate ROC to array of pads on wafer

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Readout chip connections

Use bump-bonding technique to mate ROC to array of pads on wafer

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Silicon detector layout considerations
· DC coupled detectors are simple (cheap) ú Used at LEP with AMPLEX-type preamp design ú OK as long as leakage currents small and stay small ú Straightforward layout uses two metallization layers (OK) ú Maximum pixel-readout trace crosstalk is 0.5% (6 _m strip width and 3 _m oxide) AC coupled also possible ú Avoid inputting leakage current to preamp ú More complicated
· · · · Complete additional network (hard) Additional layer and vias Cap. breakdown Beware hierarchy of capacitances
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·

fi DC


Electronics...New: Timing
· Dynamic range: MIPs to Bhabhas ú 500 GeV Bhabha/MIP 2000 (1 pixel) ú Want to maintain resolution at both ends of scale Timing: What do we need? ú NLC: 270 ns bunch trains ­ Do we need to resolve cal. hits within a train? ú Bhabhas: 15 Hz for >60 mrad at 1034 ú What about 2-photon/non-HEP background overlays? ú Exotic new physics signatures
Ref

High Gain Shaper

Mux

·

Low Gain

12 bit ADC

Logic Threshold Ramp

200 ns 8.3 ms

fi Can try to provide timing for each pixel
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Is 10 ns resolution sufficient ?
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Radiation
· EM radiation dominated by Bhabhas (in forward endcap) ú d_/dq 10 pb/q3 for t-channel ú Consider 1 ab-1, 500 GeV, shower max., and q=60 mrad (worst case)
· Use measured damage constant (Lauber, et al., NIM A 396) fi 6 nA increase in leakage current per pixel

· ·

ú Comparable to initial leakage current ú Completely negligible except at forward edge of endcap Evaluation of potential neutron damage in progress A 300 GeV electron shower into a readout chip? ú "Linear Energy Threshold" (LET) is 70 MeV/mg/cm ú 1 MIP in Si: 1.7 MeV/g/cm2 fi Expect no problems (check)
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Heat
· · Does integrated design imply fancy cooling system? Consider: NLC duty cycle is 5x10-5 (5x10-3 for TESLA)
· 270 ns bunch trains at 150 Hz

fi Use power pulsing of the electronics · For example, GLAST-equivalent readout would produce only about 1 mW average power per 1000-channel chip · Assumes power duty cycle of 10-3
... this factor is an important R&D item

·

·

Current proposed scheme: ú Heat conduction thru thick (6 oz) Cu layer in G10 m-board to fixed temperature heat sinks at edges of ECal modules Requires R&D to demonstrate
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EGS4 Model

· ·

·

·

Why? Check Geant4. (Thin sampling layers (Si) tricky.) Longitudinal ú Energy resolution ú Sampling/cost optimization Transverse ú Effective Moliere radius ú Dynamic range Hit occupancy for Bhabhas

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Standard SD: 30 Layers, 20 X
50 GeV electrons

0.

Total Absorbed Energy

Total Energy in Si

sE / E 0.16 / ÂE

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Effective Moliere radius
·Standard SD: 5x5 mm2 pixels with (1) 0.4mm or (2) 2.5mm readout gaps. ·10 GeV photons; look at layer 10

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(contd)

0.4 mm gap

2.5 mm gap

dx = 0

+ 1 pixel

+ 2 pixels

+ 3 pixels

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Alternative Sampling Configurations
50 GeV electrons

SD: 30 x 2/3 X

0

SD vB: 20 x 2/3 X0 + 10 x 4/3 X · better containment · poorer sampling

0

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Global simulation studies needed
· Transverse segmentation and effective Moliere radius ú EFA jet reconstruction, dummy ú Tau and g reconstruction ú Bhabha acolinearity Longitudinal configuration ú Number of layers (~1M$ / layer) ú vs EM resolution (not now limiting jet resolution) ú vs pattern recognition:
· Recognize hadronic showers · Track MIPs · EM shower containment

·

·

Background overlays _ timing requirement

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"Technical" simulations planned/in progress

·

Geant4 vs EGS4 ú Confirm basic description for Si/W ú B field on/off ú Compare with data (e.g. OPAL luminometer) Dynamic range

· · ·

Â

Distribution of hit occupancy in a detector wafer for jets SPICE: S/N, crosstalk, timing, etc. Â

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Status and Plans
· "Current" year ú Specify silicon detectors for technical prototype studies  · out for bids ú Qualify detectors; B field test ú Design and fab. initial RO chip for technical prototype studies
· Readout limited fraction of a wafer ($) · Bump bonding; finalize thermal plans

·

ú Begin tungsten specifications/bids Next year ú Order next round of detectors and RO chips ú Design and begin fab. of prototype module for beam test
· Full-depth, 1-2 wafer wide ECal module

·

Next-next year: ú 3rd round of detectors and RO chips ? ú Begin test beam studies (2005-ish)
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