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Time and signal pro cessing using solid state detectors
David Strom н University of Oregon

╖ Intro duction ╖ Semiconductor detector characteristics ╖ Electronics limitations

╖ Exp ectation for trackers ╖ Lab studies ( Calorimeters) ╖ Toy Monte Carlo studies (Calorimeters)

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Much of this work was carried with the help of the Si-W calorimeter group:

Si-W work н p ersonnel and resp onsibilities
M. Breidenbach, D. Freytag, N. Graf, G. Haller,O. Milgrome SLAC Electronics, Mechanical Design, Simulation R. Frey, D. Strom UO+ Si Detectors, Mechanical Design, Simulation V. Radeka BNL Electronics

+

Oregon students: J. Baumgardner, E. Fitzgerald and T. Neely mistakes and errors are mine

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Intro duction Time tagging sufficient for low o ccupancy 1 a SNR 1 - SNR = 50ns, SNR=15, a = 3: t = t = 4.7 ns
pulse height

Uncorrected tag time
100

threshold
200 300 400 500

Time (ns)

Short shaping needed for high o ccupancy (e.g. Pair monitor, n.b. signals very large here.)
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Pulse shaping = 0.5 ns
2 4 6 8 10 Time ns

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So far only Si has b een deployed in HEP exp eriments for p osition and energy measurements:
╖ Well develop ed technology ╖ Largest charge signal

GaAs was considered, but not used by LHC exp eriment. One challenge is impure structure (short carrier lifetime). CVD diamonds, not yet used in an HEP exp eriment but:
╖ Large mobility for b oth holes and electrons ╖ Uniform field (no depletion region) ╖ May now b e commercially available in the US

except as radiation detectors.

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Prop erties of Semiconductor Detectors Si Drift Mobility Electrons Holes Dielectric Constant Mean energy for electron-hole creation (eV) Density (g/cm3) Charge/╡m (electrons) (collected in exp eriments) Notes:
a

GaAs 850 32 12.9 4.35

Diamond 180 120 5.7 13.1

╡m/ns V /╡m

145 45 11.9 3.63

2.33 80

5.32 33a

3.52 35b

(i) Typical field from bias voltage is 0.5 - 1.0 V/╡m. (ii) Dielectric constant imp ortant for detector capacitance
b

NIM A 388 (1997) 408.

NIM A 514 (2003) 79.

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Charge Collection Times ╖ All materials can b e biased to b e fast enough for time tagging (300 ╡m thick material) Material Vdepletion Vbias Ideal charge collection time Holes Electrons 11 ns 15 ns 3.8 ns 3.2 ns 0.6 ns 2.5 ns

Si GaAs Diamond

80V 80V -

200 V 200 V 200 V

Assumes GaAs b ehaves as Si, reality is more complicated, see hep-ex/9509011.

╖ Charge collection times can b e decreased by using impure material (e.g. GaAs electron lifetime of 1ns have b een rep orted) ╖ For the pair monitor typical signals are 103 larger and only a fraction of the charge must b e collected. This can b e accomplished by using thin or impure materials.
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Electronics Consideration Most sources of electronics noise have

1 1 ENC Cin SNR where is the shaping time of the amplifier and Cin is the input capacitance. Thus 1 t = a SNR 1 - SNR provided the S N R >> a Cin

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For charge amplifiers: Cin(Cout + Cf ) gmCf

Cf -gm Cout

where gm is the transconductance

Cin Vbias

3/2 Thus t Cin Cin Obviously we want to decrease Cin gm can not b e increased indefinitely to comp ensate for large Cin: ╖ For CMOS capacitance of input FET will eventually dominate Cin. ╖ For bip olar base current from input transistor dominate noise.

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Noise contribution of an FET Amplifier The noise from the input FET of the amplifier is Cin 21 4K T E N CF E T = qe 3gm 4 Numerically E N CF E T 320Cin 1 gm

for Cin in pF, gm in mS and in ns. If the only significant source of noise is from the CMOS input transistor gm t
3 Cin 2 gm

Since gm is at most Idrain from an analog p ower p oint of view we are b etter off by making more small capacitance cells than a few large ones.
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Noise contribution of bip olar logic (e.g. SiGe) For a bip olar transistor Icqe gm = KT Numerically gm 40Ic Cin 1 E N Ccollector = 2qeIc gmqe 4 E N Ccollector 44Cin I1 c

for Ic in mA, Cin in pF and gm in mS. But, shot noise due to the base can b e large, esp ecially if one integrates for an entire bunch train: E N Cbase Numerically E N Cbase for int in ns and Ic in mA.
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Icint qe Icint
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2500

10

Another imp ortant effect is the contribution of the base spreading resistance (note that strip resistances will add a similar term): Cin 1 E N CRb = 4 K T Rb qe 4 For Rb in s and Cin in pF: E N CRb = Conclusion: 13Cin Rb

╖ CMOS electronics will probably b e used for low o ccupancy regions

╖ Bip olar SiGe lo oks attractive for short shaping time and high o ccupancy
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Limitation on strip length In tracking detectors the input capacitance will b e dominated by the interstrip capacitance and the capacitance to the substrate. For pitch p, strip width w, and silicon thickness d, the capacitances, in pF/cm, are approximately: Cintr 1.6 w+20 pF/cm p Csub
p 1.1 d pF/cm

Cintr taken from CMS н interstrip capacitance dep ends on radiation and detail of implants, c.f. IEEE TNS 42 (1995)42. Subsequent calculations include higher order terms for C
sub

The resistance/length of the Al strips of width w and thickness h is 275 Rs = /cm (w, h in ╡m) wh In general strips much thicker than 1-2 ╡m are difficult to pro duce.
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Assuming a p erfect CMOS amplifier with gm = 2.5mS or gm = 10mS and Cg s = 10pF, we can now plot the ideal strip time resolution versus strip length, varying w to its minimum. Minimum w typically 10-15╡m for gm = 2.5mS and 1 ╡m thick strips.
Timing Resolution 7 6 5 4 3 2 1 5 10 15 20 25 30 L cm 1 5 10 15 20 25 30 L cm 3 2 ns Timing Resolution 5 4 ns

1 ╡m thick strips
upp er curve 2.5mS, lower 10mS

2 ╡m thick strips
upp er curve 2.5mS, lower 10mS

╖ Since there will b e other sources of noise, these curves are lower limits on the timing resolution ╖ Strips 10 cm long lo ok p ossible (just fits on a 6in wafer) ╖ Strips 20 cm long might b e p ossible for 2╡m thick Al strips
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A note on p ower: warm versus cold ╖ An example: ECAL CMOS Front end electronics, 1024 channels, total time to ramp up and down: 9╡s. ╖ Instantaneous p ower is high, but avarage is low:
Instantaneous Analog charge amp 1000 mW Average Warm 1.1 mW Average Cold 5.0mW

Power pulsing allows for low average p ower. ╖ Average digital p ower and standby analog p ower dominates ( 30mW) ╖ Instantaneous analog p ower in warm machine can b e increased with small impact
Average digital p ower dep ends on total numb er of ADC conversions, this is likely to b e similar for warm and cold. If ever bunch crossing is digitized, it will b e much larger for cold. Victoria 2004

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Si-W Calorimeter Concept ECAL

Inner Tracker

1.25m

Rolled Tungsten

Circuit Board

Transverse Segmentation ~5mm 30 Longitudinal Samples 1/2 Energy Resolution ~15%/E
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3.6 Meters 1.1-1.3 Meters

Silicon Wafers
Layer Assembly

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Silicon Concept

╖ Readout each wafer with a single chip ╖ Bump b ond chip to wafer ╖ To first order cost indep endent of pixels /wafer ╖ Hexagonal shap e makes optimal use of Si wafer ╖ Channel count limited by p ower consumption and area of front end chip ╖ May want different pad layout in forward region

Front End Chip

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Silicon Design Details

╖ DC coupled detectors (avoids bias resistor work) ╖ Two metal layers

net-

╖ Keep Si design as simple as p ossible to reduce cost ╖ Cross talk lo oks small with current electronics design ╖ Trace capacitances (design: max 15pF ) are bigger than the 5pF pixel capacitance

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Factors limiting capacitance ╖ Oxide thickness, trace width:
Oxide SiO2 SiO2 SiO2 SiO2 ONO Oxide thickness 3-5 ╡m 4-5 ╡m 4╡m 5 ╡m 1.2 ╡m Trace width 6-8 ╡m 6 ╡m xxx 8 ╡m 12╡m Group CLEO I I I DELPHI H1 Belle Phob os Si Manufacturer Hamamatsu Hamamatsu CSEM Hamamatsu ERSO(Taiwan)

Ideal (next prototype)
╖ Trace length (not ideal in first prototyp e) subsequent calculations assume max length 1 7cm (R = 350 )

st Prototype

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Electronics Design

╖ Novel design due to D. Freytag uses two different feedback capacitors (NB: same scheme indep endently develop ed by the Pamela cosmic ray group in Italy) ╖ 5 to 10ns timing p ossible ╖ Current in input transistor pulsed, duty cycle < 10-3 ╖ Exp ect p ower << 40mW/wafer ╖ For large signals: C
ef f

Gain т 10pF

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Some lab measurements ╖ Uses Hamamatsu detectors with almost same design as LC detectors. Total capacitance much larger (40 to 50)pF due to cables and larger pad size. ╖ Readout electronics has similar prop erties to LC electronics, but somewhat larger gm (precise value not known). ╖ Noise term from series resistance not precisely known ╖ Overall signal to noise is 15

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Infrared laser results (pulse shap e very similar to cosmic rays):
140 135 130 125 120 115 110 105 100 95 90 Mean time (ns)

40V Bias 80V Bias 120V Bias 200V Bias

0

0.5

1

1.5

2

2.5

3 3.5 Pulse height (mips)

10 9 8 7 6 5 4 3 2 1 0

Sigma (ns)

40V Bias 80V Bias 120V Bias 200V Bias

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2 2.25 2.5 Pulse height (mips)

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Pulse Rise Times and Collection Times Bias voltage 40 80 120 200 V V V V 37. 25. 27. 25. 5 6 3 1 ▒ ▒ ▒ ▒ 0 0 0 0 . . . . 2 1 1 1 ns ns ns ns Theoretical collection time electrons holes 8.2 ns 25.6 ns 5.2 ns 15.9 ns 3.0 ns 9.3 ns

(Errors statistical only)

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Time walk correction p ossible
130 125 120 115 110 105 100 95 90 85 80 Mean time (ns)

Before corr After corr

0

0.5

1

1.5

2

2.5

3 3.5 Pulse height (MIPs)

10 9 8 7 6 5 4 3 2 1 0

Sigma (ns)

Before corr After corr

0

0.5

1

1.5

2

2.5

3 3.5 Pulse height (MIPs)

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╖ Very large signals also have go o d resolution ╖ 6 MIP energy dep ositions are common in GeV showers

2000 Constant Mean Sigma

152.3

1750

/ 25 1822. 93.59 0.6237

1500

1 GeV Photons

1250

1000

750

500

250

0

88

90

92

94

96

98

Energy of Max Pixel (MIPs)
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100 Time (ns)

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Entries Mean RMS

74 0.3108 4.395

Entries Mean RMS

74 3.369 3.370

10

12

Results for cosmic ray coincidence of 1 cm2 pads with 0.25cm x 2cm detector -
8

10

8

Resolution is 3.4 ▒ 0.4ns, b etter than 5ns goal.

6 6 4 4

The plot shows coincidences with b oth pulse heights at least 0.58 MIPs.

2 2

0

-20 0 20 Uncorrected time resolution (ns)

0

-20 0 20 Corrected time resolution (ns)

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Toy Monte Carlo Studies of Timing Resolution for 30 Samples Assumptions:
╖ Each MIP has 30 samples at random distances from the read-out chip ╖ Threshold for timing measurement is 8,000 electrons. ╖ Input FET has gm = 1.5mS and the noise contribution from the rest of the amplifier is equal to input FET. ╖ Maximum trace length 7cm (350, 15pF) ╖ Time constant for charge measurement is 200 ns. ╖ Time constant for the time measurement is 50 ns (Fixed). ╖ The noise signals in the timing and charge circuits are uncorrelated ╖ Random 5% channel to channel variation in threshold ╖ Random 1% event-to-event variation in threshold ╖ Random 5% uncertainty in constants used for correction. ╖ Reject time measurements far from mean
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Results of truncated mean for 30 samples

Number

Entries Mean RMS

10000 -0.2480E-02 0.7232

2500

2000

1500

1000

500

0

-20

-15

-10

-5

0

5

10 15 20 Reconstructed Time (ns)

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Conclusions: A Si tracker with 5 layers and 10 cm strips can pro duce a time measurement of 1 ns resolution for tracks. Present design of calorimeter electronics seems up to the job and can pro duce a measurement of with b etter than 1 ns resolution for MIPs. ╖ Need to demonstrate with ASIC prototyp e Design of the silicon detectors requires some additional optimization for timing. Impact of cross talk on time resolution needs more study.

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