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Silicon/Tungsten ECal for SiD ­ Status and Progress
Ray Frey University of Oregon ICLC Paris, April 22, 2004

· Overview (brief) · Current R&D
detectors electronics timing

· Hybrid Status from K.U. · Summary

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SD Si/W
M. Breidenbach, D. Freytag, N. Graf, G. Haller, O. Milgrome Stanford Linear Accelerator Center R. Frey, D. Strom U. Oregon V. Radeka Brookhaven National Lab

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Concept

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Wafer and readout chip

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SiD Si/W Features
Current configuration:

· "Channel
· · · · ·

count" reduced by factor of 10

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· 5 mm pixels · 30 layers: ·20 x 5/7 X0 + ·10 x 10/7 X0

Compact ­ thin gap ~ 1mm Moliere radius 9mm 14 mm Cost nearly independent of transverse segmentation Power cycling ­ only passive cooling required Dynamic range OK Timing possible

Low capacitance Good S/N Correct for charge slewing/outliers

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Electronics requirements
· Signals <2000 e noise Require MIPs with S/N > 7 Max. signal 2500 MIPs (5mm pixels) Capacitance Pixels: 5.7 pF Traces: ~0.8 pF per pixel crossing Crosstalk: 0.8 pF/Gain x Cin < 1% Resistance 300 ohm max Power < 40 mW/wafer power cycling
(An important LC feature!)

·

· ·

·

Provide fully digitized, zero suppressed outputs of charge and time on one ASIC for every wafer.
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Electronics scheme

­ old (~1 year ago)
Ref

· Dynamic range
0.1 to 2500 MIPs Requires large Cf = 10 pF on input amplifier Two ranges Requires large currents in next stages Requires small signals for ~MIPs after 1st stage T im e Pile-up background
Exotic physics In this version, expect 10-20 ns
200 ns High Gain Shaper

Mux

Low Gain

12 bit ADC

Logic Threshold Ramp

·

8.3 ms

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Electronics design Single-channel block diagram
Note: Common 50 MHz clock

­ Present

·

Dynamically switched Cf (D. Freytag) Much reduced power · Large currents in 1st stage only Signals after 1st stage larger · 0.1 mV 6.4mV for MIP

·

T im e
No 4000e noise floor Can use separate (smaller!) shaping time (40 ns) Readout zero-crossing discharge (time expansion)

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Electronics design (contd)
· Present design gives: Noise = 20-30 e/pF · Cin = pixel + traces + amplifier 5.7pF + 12pF + 10pF 30 pF Noise 1000 e (MIP is 24000 e) · Ti · · · ming: 5 ns per MIP per hit D. Strom MC (next) Simulation by D. Freytag Check with V. Radeka:
"Effective shaping time is 40ns; so 40/(S/N) 5 ns or better."

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Timing MC
D. Strom, Calor2004

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Timing MC (contd)

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Timing MC (contd)
50 ns time constant and 30-sample average

Concerns & Issues: · Needs testing with real electronics and detectors · verification in test beam · synchronization of clocks (1 part in 20) · physics crosstalk · For now, assume pileup window is ~5 ns (3 bx)

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Power

·

·

Use power cycling (short LC live times) to keep average power in check 40 mW and no Cu look to be the realistic options

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Power (contd.)

· < 40 mW per wafer (103 pixels) Passive cooling by conductance in W to module edges T 5° from center to edge Maintains small gap & Moliere radius
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Power (contd.)
Ele ctronics Duty Factor
0. 1

Duty Factor

Warm Tr= 1 mic ros ec 0. 01 Cold Tr= 1 mic ros ec W arm Tr= 10 mic ros ec Cold Tr= 10 mic ros ec

0. 001 0. 001

0. 01 Off/On Pow e r Ra tio

0. 1

M. Breidenbach, SLAC ALCPG WS

·

Even though accelerator live fractions are 3â10-5 (warm) and 5â10-3 (cold), current electronics design parameters give small difference
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Maintaining Moliere Radius

·

·

Shouldn't need copper heat sink if present heat load estimates are correct (or close to correct). Angle = 11 mrad Compare with effective Moliere radius of 3mm at 1.7m (CALICE?): Angle = 13 mrad Capacitors may be biggest challenge
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·


Components in hand

· · · ·

Tungsten Rolled 2.5mm 1mm still OK Very good quality < 30 µm variations 92.5% W alloy Pieces up to 1m long possible

Silicon · · · Hamamatsu detectors Should have first lab measurements soon (Practicing on old 1cm dets.)
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Investigation & Design Optimization of a Compact Sampling ECAL with High Spatial, Timing and Energy Resolution
Contact Person : Graham Wilson, Univ. of Kansas · Objective: Develop a cost and performance optimized ECAL design which retains the performance advantages of the Si-W concept, but finer sampling, excellent time resolution and cost which permits placement at larger R. · Investigating and comparing sampling geometries ranging from Si-W to Scintillator-W with particular emphasis on hybrid Scintillator-W-Si arrangements.

Tile-fiber considered main Scint. technology 18 option


Relevance to detector design/physics performance
· Improvement in the ECAL performance in terms of :
­ i) energy resolution (15%/E to 10%/E) ­ better single particle measurements and jet energy resolution. ­ ii) timing resolution ­ can resolve NLC bunch crossings (1.4ns separation) and reduce pile-up ­ iii) cost at fixed radius ­ allows placement at larger radius which improves angular resolution (and hence jet energy resolution) and allows gaseous tracking. ­ iv) position resolution ­ better angular resolution and jet energy measurement with particle flow algorithms
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Results
Dependence of jet energy resolution on ECAL E-resolution Extensive study of EM energy resolution for various longitudinal configurations which retain small Moliere radius Light yield of > 4 pe/mip/mm required

Hybrid sampling works :(even improves E-resolution due to negative correlations)

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Position resolution for 1 GeV of 300 µm, with 1 mm Si 20 strips at conversion point.


SiD Si/W Status and Plans
· Note that current design is optimized for warm, but could be optimized for cold Would require digital pipeline Still good to have timing? This year Qualify detectors Fabricate initial RO chip for technical prototype studies
· Readout limited fraction of a wafer ($) · Bump bonding; finalize thermal plans

·

Consider technical beam test
· Test readout, timing

Continue to evaluate configuration options
· Layering, segmentation

·

Next year (2005) Order next round of detectors and RO chips
· Might depend on ITRP decision

Design and begin fab. of prototype module for beam test
· Full-depth, 1-2 wafer wide ECal module
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Effective Moliere radius
·Standard SD: 5x5 mm2 pixels with (1) 0.4mm or (2) 2.5mm readout gaps. ·10 GeV photons; look at layer 10

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(contd)

0.4 mm gap

2.5 mm gap

dx = 0

+ 1 pixel

+ 2 pixels

+ 3 pixels

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Alternative Sampling Configurations
50 GeV electrons

SD: 30 x 2/3 X0

SD vB: 20 x 2/3 X0 + 10 x 4/3 X · better containment · poorer sampling

0

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Radiation
· EM radiation dominated by Bhabhas (in forward endcap) d/d 10 pb/3 for t-channel Consider 1 ab-1, 500 GeV, shower max., and =60 mrad (worst case)
· Use measured damage constant (Lauber, et al., NIM A 396) 6 nA increase in leakage current per pixel

· ·

Comparable to initial leakage current Completely negligible except at forward edge of endcap Evaluation of potential neutron damage in progress A 300 GeV electron shower into a readout chip? "Linear Energy Threshold" (LET) is 70 MeV/mg/cm2 1 MIP in Si: 1.7 MeV/g/cm2 Expect no problems (check)
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