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L1 Simulation Roadmap

Brief Summary of L1 Simulation Upgrade

February 19th, 2004 BaBar Collaboration Meeting SLAC

Eric Torrence University of Oregon

Eric Torrence

1/12

February 2004


New Since December

First production code contributed!
Release 14.3.0 and greater · L1DctData modified L1DTsfDigi, new L1DZpdDigi · L1DctOnline Abstract interface for TSF LUT

All interfaces with "outside world" ~ 20 packages in total i.e. L1TFMon, L3, OepSequences, ...

Remaining L1Sim changes are (mostly) inside the "black box"

Online Build not needed? (yet...)

Eric Torrence

2/12

February 2004


Phase 0 (Now)

DchDigis

EmcDigis EmtSim

trgDC

L1Accept

This IS the current SP6 (14.3.X)

Base simulation code unchanged, only the interface elements (Digis, TsfLUT)

Eric Torrence

3/12

February 2004


Phase I

DchDigis TsfSim BltSim PtdSim

EmcDigis EmtSim

Glt Interface GltSim Deployed Validated Written Not written L1Accept

Significant upgrade to L1 Simulation Could be deployed in SP6 to improve simulation of Run4 data Time estimate?? (~2 months)
Eric Torrence 4/12 February 2004


Phase II

DchDigis TsfSim BltSim PtdSim BltSim ZpdSim

EmcDigis EmtSim TrigConfig

Glt Interface Deployed Validated Written Not written GltSim L1Accept

Full L1Sim upgrade needed for hardware change In principle can be ready shortly after Phase I completed (and validated) Real work needed in TrigConfig (best to leave to Эberexperte)
Eric Torrence 5/12 February 2004


Code Validation

Real concerns for how to validate (old) simulation code/boards

Possible Options · Teststand · Real Data · trgDC comparison · Data-MC comparison

Each has advantages/disadvantages

Probably no single one is sufficient Real work to be done here...

Eric Torrence

6/12

February 2004


Teststand Validation

Simulation Board In BoardSim Board Out

Teststand Input Mem Hardware Output Mem

· Load arbitrary or simulated bit patterns into board memories · Compare with simulation expectation Advantages Bit-level comparison Disadvantages Cumbersome, need good input patterns, hard to test "system" problems Possible to extend to multi-board?

Eric Torrence

7/12

February 2004


Real Data Validation

Simulation Input Data BoardSim Output Data

XTC File Input Data Hardware Output Data

· Use real data taken in IR2 · Compare hardware result with simulation Advantages Proper event mix Could be run continuously (trickle stream) Disadvantages Bit-level not possible Meaningful comparisions not obvious

Eric Torrence

8/12

February 2004


trgDC Comparison

DchData newSim Output Data trgDC Output Data

· Start with DchDigis (real or simulated) · Compare parallel simulation output Advantages Straightforward to implement Tests "whole system" Disadvantages Don't necessarily want agreement! Not a direct validation of the hardware

(The plan is to actually improve something...)
Eric Torrence 9/12 February 2004


Data-MC Comparison

DchData Simulation Output L1 Hardware Results

· Start with real data (XTC file) · Compare high-level "physics" output Advantages Straightforward to implement Tests "whole system" Test quantities that really matter? Disadvantages Limited comparisions available (L1A) Will not find all problems Will never find rare/subtle differences
Eric Torrence 10/12 February 2004


Simulation Tools Moose · Ultimately where we want this to run... · Add new modules to L1SimL1TrigSequence This works, although is cumbersome for detailed debugging

Bogus/SimApp model · Matthias Steinke working on "Kangerized" versions · Can then generate Bogus data and repeatedly run simulation (as before) Need to define L1DctDataK

Teststand convertor · Translate simulated data into memory maps · Works for TSF, possibly ZPD? Needs work for multi-board Is this really useful?
Eric Torrence 11/12 February 2004


Well past time to get this finished!

Simulation can still beat hardware (4 years too late for Runs 1-3...)

Eric Torrence

12/12

February 2004