Not only are the CCD Transfer Curves useful for characterization, they also serve as an invaluable tool for the optimization of the CCD's clock waveform and biases. This section contains a description of the CCD Transfer Curve method of CCD optimization and provides CCD Transfer Curve data used to determine the ideal operating parameters of the PlutoCCD CCD. All CCD performance characteristics depend on camera clock drive, bias, and off-ship signal processing parameters. Rather than use a trial and error approach to CCD optimization, Jim Janesick, Chief Scientific Officer for PixelVision, Inc., developed the CCD Transfer Curve method for CCD optimization. The approach is detailed below and is described in more detail in Janesick, James R., "CCD Transfer Curve Method - Standard for Absolute Performance of CCDs and Digital CCD Camera Systems", SPIE, San Jose, February 1997.

A diagram of the output register of the PlutoCCD CCD is shown in Figure 5-1 and illustrates the setup clock waveform and DC potentials for the last three pixels of the serial shift register (V_f), before it is collected in the Summing Well (V_sw), transferred to the Last Gate (V_otg), and then sampled by the output MOSFET, when the charge is dumped to the output node using the amplifier with a Voltage Reference (V_ref), Reset Gate (V_rg), and output drain (V_dd). This picture provides a visual aide that assists in the understanding of the methodology used to optimize PixelVision’s CCDs.

5.1 Output Transfer Gate (OTG) Transfer Curve: The last gate (the output transfer gate, OTG) is the first critical voltage that is set when optimizing and characterizing the PlutoCCD CCD. It is the voltage that is used to set all of the other CCD clock and bias voltages. The threshold potential (V_eff), is a CCD constant that is used to determine the maximum channel potential (V_max), beneath a gate electrode when it biased to V_g. The channel potential well beneath a gate electrode extends 3.5 to 4.5 microns into the silicon. Maximum potential (V_max), is at its maximum near the surface where signal electrons are first collected. The collecting phase is the phase which is biased high (say 3 volts) and collects photoelectrons. The barrier phase is biased low (say to –8 volts) and confines charge to the collecting phase. V_eff, the maximum channel potential, is found from the OTG Transfer Curve.

When the potential of the Output Transfer Gate (OTG) is elevated, the channel potential will increase linearly until it becomes equal to the potential of the sense node that physically overlaps the region. Due to the sampling process, the channel potential is reset to V_ref when the Reset Gate is switched on. When the maximum channel potential (V_max) is greater than the reset voltage (V_ref), then the electrons from the sense node will flow under the Output Transfer Gate because its potential is lower. When V_max > V_ref, the electrons flowing under the Output Transfer Gate will result in "charge injection" into the CCD. The breakpoint is called "clock punch-through" because of the sudden clock feed-through signal that is observed at the output of the CCD.

Before V_otg can be set to a specific voltage potential, one other important breakpoint for the CCD is required. When a phase is driven sufficiently negative, the surface potential at the Si-SiO₂ interface will eventually reach the same potential as V_sub, which is normally set to 0 volts. When this occurs, holes from the substrate and surrounding p+ material populate the interface and "pin" the surface potential to the substrate potential. This state is called "inversion" (V_inv), because majority of carriers for n-material, which are used to dope the material, are electrons. Under these conditions, the potential at the surface and throughout the silicon is fixed and is independent of the gate voltage applied.

Knowing V_eff, V_inv, and V_ow, the "operating window" of the bias points that accommodated device and process variation, puts one in an excellent position to select the other CCD operating parameters one-by-one. The Output Transfer Gate is set to an operating range that centered in the operating window, V_ow, above the onset of inversion.

5.2 Amplifier Voltage Reference / OTG Transfer Curve & V_dd/V_rd Transfer:

For the ADAPTIII CCD, it can be seen that if the Output Transfer is set to –4 volts, then the optimal amplifier noise can be achieved with the voltage settings of V_dd = 24 volts, and V_rd = 13.5 volts.

Amplifier noise was measured with the CCD cooled to 250K and the charge clocked away from the output amplifier. After optimizing the Output Transfer Gate voltage, in a method similar to that discussed above, the noise of the amplifier was measured as a function of the Reset Gate of the output amplifier. As is shown in Figure 5.2-1, above a V_rd voltage setting of 11 volts the amplifier completely resets and noise decreases. Tests demonstrated that the "high" rail of the Reset Gate is optimally operated above 13 volts to provide a complete reset. Choice of the V_rd setting must take into account the signal swing as well as processing variation. For this reason, a voltage setting of 13.5 volts was used – assuming a 2 volt signal swing and an operating process window of 13.5 volts. Next, the optimal V_dd setting was chosen by plotting noise versus V_dd voltage settings. Although the gain of the output FET increased with increasing V_dd to V_rd voltage (see Figure 5.2-2), the noise floor starts to increase when the charge carriers reach the surface close to the gate Si-Si0₂ interface. This point is represented by the knee of the curves in Figure 5.2-3. Shown in Figure 5.2-3 are the V_dd/V_rd Transfer Curves for three gate-to-drain (V_rd) settings. A V_rd setting of 13.5 volts exhibits optimal noise performance. The amplifier voltage reference is set to a potential just above (taking into account V_ow) the onset of clock punch-through. In addition, extra latitude is given V_ref because the potential in the sense node, due to signal charge, moves in the direction of punch-through when charge is in it. As signal swings can often exceed 2 volts, sufficient margin must be given when setting the operating voltages to accommodate the largest signal swings required of the application as well as processing variations.

These transfer curves are generated for each manufactured CCD lot to verify that the operating conditions of the electronics are optimized for the operating window offered by the CCD process.