A. Architecture

Fig. 1 shows the overall architecture of the CPS32. The sensor portion of the chip consists of a 32x32 array of pixels on 26.4µm centers, with each pixel containing a 9.6µm x 13.2µm p-n diode detector, an amplifier and a multiplexer switch to the column bus. The outputs of the columns are multiplexed to an output buffer, and address decoding is performed by digital support circuits. This constitutes a basic Active Pixel Sensor. The chips were fabricated through the MOSIS fabrication service using the 1.2µm Hewlett-Packard n-well process. This is a standard, commercial CMOS process with LOCOS isolation, an unhardened 21 nm gate oxide, and a 500 nm field oxide.

Figure 2 shows a more detailed representation of the signal path from the detector to the output. The detector is reset by a transistor switch, buffered by a source follower, and connected to the column bus by another transistor switch. Selection and reset are performed on a row-by-row basis. A transistor at the bottom of each column, biased by a fixed external bias, serves as a load to the selected pixel. Finally, a column multiplexer connects the desired signal to a common output source follower. Note that the pixel and column circuitry is entirely p-channel, while the output buffer is
n-channel.

In addition to the basic detector array, the CPS32 also includes pFET dosimeters [2] to measure total dose, and has additional multiplexer channels for the dosimeters and an external temperature sensor.

Because this was a first generation design, the design was kept simple, and many features were not optimized. This reduced the development risk, and allowed flexibility in selecting the operational mode. The digital logic, for example, is very simple, consisting only of address decoders. More advanced designs would include circuitry to generate all the clocking signals, and might include event discrimination to reduce the load on the instrument processor.

The analog processing in the CPS32 is likewise simple. While other APS designs [3] incorporate storage capacitors at the bottom of each column to facilitate correlated double sampling (CDS) or signal-minus-reset processing [4], these were not used for the CPS32 because the capacitors were expected to be sensitive to particle events. This would interfere with particle spectrometry, where the desired signal consists of a few events in an otherwise dark background. Such interference also occurs in APS imagers (and all other imagers as well), but it generally represents a small fraction of the data and is either ignored or removed by image processing.

B. Operation

In operation, the pixels are reset, one row at a time, by turning on the reset transistors. This places a reverse bias on the detector diodes. Any charge generated during the integration time, due to particle events, photocurrent or dark current, will be integrated on the diode capacitance. At the end of the integration time, the pixels are sequentially selected for read out. Because of the buffering provided by the source followers, the readout can be non-destructive, allowing signal processing functions such as correlated double sampling and multiple sampling [5]. Even with the simple built in digital circuitry, the only timing signals needed are the row and column addresses and the reset clock.

C. Comparison to IR Multiplexers

The design of the CPS32, as described above, is identical that of a standard source-follower-per-detector (SFD) infrared multiplexer [4]. There are, however, significant differences from a radiation perspective. First, the detectors in the CPS32 are monolithically integrated diodes, rather than separate infrared detectors. Therefore, the radiation hardness of the detectors is limited to that which can be obtained within the CMOS process.

The main difference, however, is in the operating temperatures. Narrow bandgap infrared detectors need to be operated at cryogenic temperatures to reduce their dark current, and so the multiplexers are also operated cold. This significantly changes the physics of the radiation effects. Additionally, any dark current sources generated in the silicon multiplexer will be frozen out. In contrast, the CPS32 will be operated at ambient temperatures. The testing reported here was performed at temperatures between -25ºC and +25ºC, with radiation exposures at room temperature.

D. Design Features for Radiation Hardness

The CPS32 pixels contain two design features intended to improve the radiation hardness. First, p-channel transistors were chosen for the pixels, with diodes fabricated as p⁺ diffusions in the n-well. This was motivated by the fact that p-channel transistors are generally reported to have lower densities of radiation induced interface states which, in turn, should result in lower increases in dark current. P-channel transistors are also not subject to radiation induced inversion in the field oxide and bird’s-beak region, nor to the increases in sub-threshold leakage seen in n-channel transistors. Such leakage would be disastrous to the charge-sensitive front end of the CPS32. Only the digital logic, the column multiplexers, and the output amplifier contain n-channel transistors, and these are all low-impedance circuits.

The second feature for radiation hardness, shown in Figure 3, is the use of an annular reset transistor, enclosing the detector diode. This fully isolates the diode, the most sensitive portion of the circuit from any possible bird’s-beak or field oxide leakage. It also means that the diode depletion region intersects the silicon surface under gate oxide, rather than under the bird’s-beak, which has a higher concentration of interface states.

There are, however, some consequences of these special radiation-hardening features. The use of diodes in the n-well means that the collecting volume is thin, as shown in Figure 3. In fact, the collecting volume is only about half the well depth, since charge generated in the lower region of the well is collected by the power supply at the substrate junction and is not sensed. Therefore, the detector measures the charge density along the track, i.e. the LET of the particles.

MOSIS does not report the well parameters that would be needed to predict device sensitivity. However, from the alpha particle sensitivity reported in Section IV, we determine that the effective collecting region is 1.2 µm thick, while capacitance values indicate a well doping level of ~2.10¹⁷ cm^-3. Both of these values are physically reasonable and imply efficient collection of the radiation-generated carriers. Although the thin collecting region results in a small signal charge, this is compensated for by the high conversion gain of the CPS32.

The use of the annular geometry results in a very wide reset transistor, with a high gate-to-source capacitance. This produces a large clock feedthrough and reduces the dynamic range. However, the annular transistor and thin collecting layer have advantages in reducing the problem of peripheral hits, discussed below.

E. Performance Characteristics

The primary performance parameter for an APS, whether used for charged particle spectrometry or for imaging, is the signal-to-noise ratio. The signal level for the CPS32 is relatively high, due to the small sense-node capacitance of ~70 fF, which is dominated by the diode. This is a consequence of breaking the detector area into small pixels, and is particularly advantageous for charged particle spectrometry, where the signal charge is independent of the pixel size and integration time.

The noise can be divided into spatial, temporal and detection components. The spatial, or fixed pattern noise (FPN), is generally the largest, consisting of variations in offset and gain from pixel to pixel. Offset variations are the result of pixel-to-pixel differences in transistor threshold voltages, clock feedthrough and dark current, while gain variations come from differences in transistor and diode parameters, notably physical dimensions and doping levels.

Temporal noise, likewise, comes from various sources. Dark current, in addition to its spatial variation, also contains temporal variations. This is usually modeled as shot noise, and is a major driver for reducing the dark current. However, as described in Section IV, we have observed an additional temporal noise in the dark current, in the form of Random Telegraph Signals.

White noise and 1/f noise come from the pixel and output source followers, and from the measurement system. The 1/f noise is particularly a problem in a photodiode APS, like the CPS32, since it is not significantly reduced by correlated double sampling, as it is in a CCD or photogate APS. This is because the measurements of the relaxed reset level and the signal level must be separated by the integration time.

Reset noise, also called kTC noise, is a fundamental thermodynamic noise in the charge on the sense node capacitance after reset, equal to ~100 e- for the CPS32. Reset noise is removed by the standard technique of correlated double sampling (CDS), which has the added advantage of removing the fixed offset components of FPN.

Detection noise is due to variability in the charge generation and detection processes. The variability of the charge generation is described by the Fano noise [6], which is a fundamental characteristic of the interaction of the particles with silicon, but it not a significant component of the CPS32 noise. Variability of the collection process occurs because the division of collection between the two junctions is probabilistic, leading to a shot noise which, for 5 MeV alpha particles, is approximately 250 e-, or 0.4%

In addition, particle hits in the periphery of each pixel will be partially collected, as shown in Fig. 3. Only hits in the region under the reset gate will be partially collected because hits in the drain region surrounding the diode will be collected by the power supply and not sensed. However, this region has an area equal to 45% of the area of the diode itself. This is a fundamental property of a small pixel size with a large perimeter to area ratio. Hits in other regions of the circuit, such as the amplifiers, multiplexers and busses will cause very small signals because of the high capacitance and low impedance of these nodes.

Finally, there are several other characteristics relevant to active pixel sensors, such as dynamic range, speed of operation, power consumption, and linearity. While we have not investigated the nonlinearity experimentally, it is expected to be ~10%, coming from the variation of the diode capacitance with voltage. In principle, it can be calibrated.