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P R E L I M I N A R Y SITe 512 x 512 Thermoelectrically
Cooled General Description The CCD is thermoelectrically (TE) cooled using a two stage cooler that is an integral part of the package. The sealed vacuum package prevents the device from collecting moisture when it is cooled below dew point temperature and prevents thermal conduction of heat to the device. SITe's unique thinning and back surface enhancement process provides increased blue and UV response in a flat and fully supported die. Thermoelectric Cooler Functional Description The signal charge collected in the imaging array is transferred along the columns, one row at a time, to the serial output register and from there to the output amplifier. Three levels of polysilicon are used to fabricate the three gate electrodes which form the basic CCD cell (pixel). All of the pixels in a given row are defined by the same three gates. Corresponding gates in each row within a group of 512 are connected in parallel at both edges of the array. The clock signals used to drive the imaging area gates are brought in from both edges of the array, thus increasing the rate at which the rows can be shifted. Serial Registers The output of the serial register is terminated in a summing well, a DC-biased last gate (which serves to decouple the serial clock pulses from the output node), and an output amplifier. The summing well is a separately clocked gate equal in charge capacity to the other serial gates. Noiseless charge summing of consecutive serial pixels. is possible using this gate. Similarly, it is possible to sum pixels into the serial register by performing repetitive parallel transfers with the serial clocks fixed. In this manner, it is possible to collect and detect as one pixel the sum of the charge in sub-arrays of the imaging section. The sum of this sub-array charge must be less than the full well charge. The well capacity of a pixel in the serial register is greater than that of a parallel pixel to ensure that the charge handling capacity is large enough for this summing operation. Output Structure A positive pulse is applied to the reset gate (RG). This resets the potential of the floating diffusion to the potential connected to the reset transistor drain (RD). The reset gate voltage is then turned off and the output node (the floating diffusion) is isolated from the rest of the circuit. The charge from the serial pixel is then transferred to the output node on the falling edge of the summing well (SW) clock signal. The addition of charge on the output node causes a change in the voltage on the gate of the output MOSFET. This change in voltage is sensed at OUT. Timing The transfer gate (TG) adjacent to the serial output register must be clocked. The upper transfer gate next to the unused serial register should be held low to prevent unwanted charge in this register from entering the parallel registers. The unused serial register's gates are not clocked. During a parallel or serial shift, the signal charge is transferred one pixel at a time. A frame readout consists of at least 512 parallel shift and serial readout sequences for a full frame. A serial readout sequence consists of at least 527 serial shifts for full frame mode (15 for each serial extended region plus 512 pixels of data from the imaging array). The serials are static when the parallels are shifting and vice-versa. During integration, the serial clock is normally kept running continuously to flush the serial register and to stabilize the bias levels in the off-chip signal chain. Multi-Phase Pinned (MPP) Operation To operate the CCD in the MPP mode, the array clocks are biased sufficiently negative to invert the n-buried channel and "pin" the surface potential beneath each phase to the substrate potential. This allows holes from the p+ channel stop to populate the surface states at the silicon/silicon dioxide interface, minimizing surface dark current generation. To enable all three phases of the array to be inverted and still retain well capacity, MPP devices have an extra implant under the phase 3 gates. During integration, this creates a potential barrier between each pixel allowing signal charge to accumulate under phases 1 and 2 at each pixel site. A consequence of this mode of operation is that the total well capacity is about 50 percent of that of a standard CCD if all the parallel clocks are operated at the same voltages. A larger well capacity can be obtained if phase 3 parallel clock high rail is operated about 3 volts higher than the phase 1 and phase 2 high rails. |