General debugging locations.

high voltage power supply building:

• 190154 sh1,2 - Schematic diagram hvps control
• 190153 sh1,3 - control assembly hvps. shows location cables,tbX, etc.
  
• 190235 sh1-5 - schematic diagram hvps control main board
• 190235 sh3 lattice fpga chip
• 190234 board chip layout
  
• 190374 logic diagram for lattice cominatorial logic.
  

Dome

• 190152 sh 1-12 System supervisor chassis sh 1-12
• Shows different boards A1-A11
• 190151 sh 1-3 shows where boards a1-a11 are located. (in parts list manual)
  
• fpga chips:
• 190223 sh 1-3 combinatorial logic. Contains fpga chips U19,U44
• 190222 -board chip layout
  
• 190362 Logic diagram for U19 chip
• 190364 Logic diagram for U44 chip.
• 190152 sh8 - A8 board.
• general connection diagram U19,U44 chips

Specific debugging:

HVPS  fpga chip

• 190154 general connections
• 190235 sh1-5   sh3 shows chip, other sheets are driver input,output
• 190374 logic page
• Debugging Ground switch:
• (see logic sheet 190374).
•  Easier to look at connected to chip since fpga pins are close together.
  
•  

  pin on chip (see 190374 logical sheet)	connects to.	description
  p5 crowbar heat lamp	U41_p4 (4050B)
  p6 crowbar blower proof	U41_p12
  p7 hvps door proof	U41_p15
  p8 hvps grnd stick	U41_p2
  p16 Dome HV ready(standby)	E8	ActiveLo
  p38 hvps breaker status (A)	U60_p11 (sh4 AD)	Active lo (output)
  p46 Reset pulse	E13 (active lo)
  p48 (B) crowbar scr. p48 is breaker coil. if not low more debugging	U64_p5 (sh4 AF)	active lo  (output)
  p51 (G) keep alive	U64_p11 (sh4 AI)	active lo (output)
  p67 hvps breaker closed	U18_p12 (4050B)
  p68 hvps AC current	U18_p4
  p69 hvps DC current	U18_p15
  p77 crowbar trigger ps proof	E4	active lo
  p83 hvps oil	U68_p6

  
  

28may12 ground switch opening

    For the venus runs in may12 the run was stopped about once a day with the ground switch interlock (on the faults page). Looking at the next page you could see
the hvps contactor open

• .There are no other faults present when this occurs.
• previously the logic that generated the ssr groundswitch signal was losing dome hv ready without a fault occurring.
  

• Note --> is signal direction toward cpu.. sometimes it was easier to write as <-- when tracking from cpu backwards.
  
• ground switch interlock: from status word 19_80
• It is read from digital input dome tti_12 xa2 hvps (schematic 109154 xa2) tti bit 08(cnt from 1)l.
  
• tracing the signal from io back
• 109154 sh 2xa2 tti bit 02(cnt from 1)outputs on p3-8."ground switch open" <- J3-6
  
• 190235 sh1 j3-6 <- chips <- j1-8 
• 190154 sh 2 xa2 j1-8 <-p1-6 Bc32 (also goes to p2-7) <- TB3-13 ground switch..
• The ground switch ssr (that closes the contactor)  is controlled by
• fpga logic on 190374 
• 190235 SH 3  pin 50 output of fpga  -> AH sh4 driver chips -> J5-7
• 190154 sh 1 J5-7  -> P5-7 -> card interface C18,R18 -> TB2-9 (to ground sw ssr relay)
• Dome hv ready (this becomes the standby signal if the hv is currently off).
  
• 190374 logic p16 input to fpga from
• 190235 sh 3 H# fiber optic receiver  (see test [point E8])
• 190154 sh1,2 fiber optics  u106

home_~phil