PDEV FPGA code

FPGA overview
directory structure

FGPA CODE (top level and main sections):

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TERMINOLOGY:

• PDEV: This is the name of the entire spectrometer. It includes the hardware and software on the spectrometer box and the file server.
  
• GX: GX refers to the signal processor  FPGA in the spectrometer. There are two FGPAs in the spectrometer usually referred to as GXA and GXB. GX is the entire FGPA. The internal design of the FGPA is broken down into separate pieces with different names. The pieces are plinth and sp.
  
• SP: The FGPA design is divided into 2 pieces. SP is the signal processing datapath in the FPGA. PDEV is designed so that SPs for other purposes can be dropped into GX  and take advantage of the rest of the system without too much effort on the part of the developer. SP sometimes refers to the default signal processor SP1.
• SP1: This is the default SP written by jeff mock.
  
• plinth: plinth is everything in the FGPA outside of the SP.  The plinth code provides a register interface to the powerPC processor in the spectrometer, a DMA interface for dumping ata , a large QDR SRAM FIFO, for buffering realtime data from the SP to the non-realtime world.
  
• PFB: Polyphase Filter Bank. This converts the time domain data to frequency domain data. It had a much better channel to channel isolation than a typical fft. It can do this by take 4 times as much data for each fft (allowing it to shape the individual channels).
  
• CMIX: A digital mixer that is part of the SP1 code. It takes the a/d sample and digitally mixes the band to a different center frequency. When used it is normally followed by the DLPF to filter and decimate the band.
• DLPF: Digital low pass filter that follows the A/D, CMIX code. It can filter and decimate the data by 2 to 1024

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FPGA OVERVIEW: (top)

    The fpga code has been modularized so that different signal processors can reuse the verilog code of the different modules. Modules are created using a two step process:

1. perl scripts generate the verilog source code.
2. The xlinix code then compiles the verilog.

    Module constants are normally defined in module/src/Makefiles.def

Module directories contain:

• sp/build : The module is created in this directory using the Makefile that is there.
• sp/src     :  Contains Makefile.defs defining the constants for this module. It also contains verilog code for this module  (xxx.v) as well as any perl scripts used to generate  verilog code.
  
• sp/cmix :  contains makefile to compile any other modules used by this module. In the sp example it has cmix and dlfp.

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Directory structure: (top)

• pdev/gx
• jfft : holds pdev (pfb), cmix, dlpf modules.
• pdev/: Makefile to make pfb
• src/   : Makefiles.def for pfb. Perl script to create pfb: mkjfft
• cmix/: digital mixer
  
• src: Makefiles.def for CMIX.  mkcmix perl script to create verilog source
• sim: Makefile to make all ??
  
• dlpf/ :  Code for DLPF module.
  
• src: Makefile.defs, mkdlpf perl script, top.v
• build: Makefile to make dlpf module
• sim: Makefile to create sim ??
• plinth: holds code that is not included in sp.
• src: verilog code for plinth as well as Makefile.defs.
• build: this directory has an .edn and .edf file but no Makefile?
• sp: the default signal processor.
• build: Makefile to build sp.
• cmix: Makefile to build cmix module for sp
• dlpf: Makefile to build dlpf module for sp
• src: Makefiles.def and xxx.v verilog files for sp.
• xilinx:
• simprims: hold xxx.v xlinix files.

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FPGA code  (top)

Funtion	Verilog file	functionality
TOP of fpga code (plinth code)	gx/plinth/src/gx.v gx/plinth/src/gx.vh some defines	top of fpga setup adcclk.v setup gpin pins get adcinput (adcpad.v, adcpad_mult.v) offset: 12 bits. scaling 16 bits - [0,2). ffff-2). 8000=1. call sp() routine pack_fifo.v interface extr sram with sp1 and pack_dat reg pi.v power pc interface to output data. pi_fifo.v Crosses boundary between adcclk/pciClk pi_data.v
SP FPGA CODE (signal Processor)
Main SP driver routine	gx/sp/src/sp.v gx/sp/src/sp.vh Some defines	main sp routine: adcinp complex mixer pfb/fft compute stokes accum power pack for output
adc input	gx/sp/src/adcin.v	Multplex a/d input map a/d -> polA,B real,Img 0 input, or select test Negate inputs if requested Count overflows
complex mixer
lowPassDigital filter	gx/sp/dlpf/rtl/xlfp.v Just the main routine.
jfft with pfb	xfft.v just the main program.
align pols for stokes computation	gx/sp/src/polalign.v
Compute Stokes	gx/sp/src/stokes.v gx/sp/src/vshift.v programmable upshift gx/sp/src/smult.v gx/sp/src/smult1.v
Accum power	gx/sp/src/acc.v gx/sp/src/acc_s.v signed accum with saturation gx/sp/src/acc_us.v unsigned accum with saturation
pack accumulator outputs	gx/sp/src/pack.v