Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/plinth/build/dcmx1y1_2vp50.edn Дата изменения: Thu Jun 26 04:26:02 2008 Дата индексирования: Sat Sep 6 20:13:49 2008 Кодировка: Поисковые слова: c 2002 x5

(edif dcmx1y1_2vp50
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2003 10 29 11 14 58)
(author "Synplicity, Inc.")
(program "Synplify" (version "7.2, Build 175R"))
)
)
(library VIRTEX
(edifLevel 0)
(technology (numberDefinition ))
(cell LUT4 (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
)
(library UNILIB
(edifLevel 0)
(technology (numberDefinition ))
(cell VCC (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
)
(library work
(edifLevel 0)
(technology (numberDefinition ))
(cell dcmx1y1_2vp50 (cellType GENERIC)
(view structure (viewType NETLIST)
(interface
(port clock1_in (direction INPUT)
)
(port clock2_in (direction INPUT)
)
(port clock1_out (direction OUTPUT))
(port clock2_out (direction OUTPUT))
)
(contents
(instance VCC (viewRef PRIM (cellRef VCC (libraryRef UNILIB))) )
(instance INV1_1 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
(property lock_pins (string ""))
(property bel (string "F"))
(property loc (string "SLICE_X40Y174"))
(property init (string "0f0f"))
)
(instance BUF2_1 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
(property lock_pins (string ""))
(property bel (string "G"))
(property loc (string "SLICE_X67Y175"))
(property init (string "ff00"))
)
(instance INV2_1 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
(property lock_pins (string ""))
(property bel (string "F"))
(property loc (string "SLICE_X67Y175"))
(property init (string "00ff"))
)
(instance INV1_2 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
(property lock_pins (string ""))
(property bel (string "F"))
(property loc (string "SLICE_X41Y175"))
(property init (string "00ff"))
)
(instance BUF2_2 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
(property lock_pins (string ""))
(property bel (string "G"))
(property loc (string "SLICE_X66Y174"))
(property init (string "ff00"))
)
(instance INV2_2 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
(property lock_pins (string ""))
(property bel (string "F"))
(property loc (string "SLICE_X66Y174"))
(property init (string "00ff"))
)
(net clock1_in (joined
(portRef clock1_in)
(portRef I2 (instanceRef INV1_1))
))
(net clock2_in (joined
(portRef clock2_in)
(portRef I3 (instanceRef INV1_2))
))
(net clock1_out (joined
(portRef clock1_out)
(portRef O (instanceRef INV2_1))
)
)
(net clock2_out (joined
(portRef clock2_out)
(portRef O (instanceRef INV2_2))
)
)
(net (rename VCCZ0 "VCC") (joined
(portRef I2 (instanceRef INV2_2))
(portRef I1 (instanceRef INV2_2))
(portRef I0 (instanceRef INV2_2))
(portRef I2 (instanceRef BUF2_2))
(portRef I1 (instanceRef BUF2_2))
(portRef I0 (instanceRef BUF2_2))
(portRef I2 (instanceRef INV1_2))
(portRef I1 (instanceRef INV1_2))
(portRef I0 (instanceRef INV1_2))
(portRef I2 (instanceRef INV2_1))
(portRef I1 (instanceRef INV2_1))
(portRef I0 (instanceRef INV2_1))
(portRef I2 (instanceRef BUF2_1))
(portRef I1 (instanceRef BUF2_1))
(portRef I0 (instanceRef BUF2_1))
(portRef I3 (instanceRef INV1_1))
(portRef I1 (instanceRef INV1_1))
(portRef I0 (instanceRef INV1_1))
(portRef P (instanceRef VCC))
)
)
(net clkd1inv_1 (joined
(portRef I3 (instanceRef BUF2_1))
(portRef O (instanceRef INV1_1))
)
(property route (string "{2;1;-5!-1;-51256;175440;14;81;416;30;13!0;9272;1615;42!1;21432;220!2;13944;-344;2!3;7832;0!4;1033;-555;0!5;327;0;4;120;419;21!}"))
)
(net clkd1buf_1 (joined
(portRef I3 (instanceRef INV2_1))
(portRef O (instanceRef BUF2_1))
)
)
(net clkd1inv_2 (joined
(portRef I3 (instanceRef BUF2_2))
(portRef O (instanceRef INV1_2))
)
(property route (string "{2;1;-5!-1;-51096;176472;14;81;419;30;13!0;9128;-1677;42!1;21416;-208!2;13960;324;2!3;7832;0!4;1008;798;0!5;176;-365;4;120;416;21!}"))
)
(net clkd1buf_2 (joined
(portRef I3 (instanceRef INV2_2))
(portRef O (instanceRef BUF2_2))
)
)
)
(property KEEP_HIERARCHY (string "TRUE"))
)
)
)
(design dcmx1y1_2vp50 (cellRef dcmx1y1_2vp50 (libraryRef work))
(property PART (string "xc2vp50ff1152-5") (owner "Xilinx")))
)