Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/sp/src/sp.vh Дата изменения: Thu Jun 26 04:27:55 2008 Дата индексирования: Sat Sep 6 19:49:20 2008 Кодировка: Поисковые слова: п п п п п п п п п

// Jeff Mock
// 2030 Gough St.
// San Francisco, CA 94109
// jeff@mock.com
//
// Copyright 2005,2006
//
// $URL: https://www.mock.com/svn/pdev/trunk/gx/sp/src/sp.vh $
// $Id: sp.vh 1021 2007-09-17 17:22:47Z jeff $

`timescale 1ns / 1ps

// Diagnostic bus register interface
//
`define CREG_ARSEL 16'd0
`define CREG_AISEL 16'd1
`define CREG_BRSEL 16'd2
`define CREG_BISEL 16'd3
`define CREG_ARNEG 16'd4
`define CREG_AINEG 16'd5
`define CREG_BRNEG 16'd6
`define CREG_BINEG 16'd7
`define CREG_LEN 16'd12
`define CREG_DIAG 16'd13
`define CREG_PSHIFT 16'd14
`define CREG_PFBBY 16'd15
`define CREG_SHIFT 16'd17
`define CREG_FCNT 16'd19
`define CREG_DCNT 16'd20
`define CREG_DSHIFT_S0 16'd22
`define CREG_DSHIFT_S1 16'd23
`define CREG_DSHIFT_S2 16'd24
`define CREG_DSHIFT_S3 16'd25
`define CREG_SCNT 16'd26
`define CREG_FMTWID 16'd28
`define CREG_FMTTYPE 16'd29
`define CREG_DUMPSTART 16'd30
`define CREG_DUMPSTOP 16'd31
`define CREG_ASHIFT_S0 16'd32
`define CREG_ASHIFT_S1 16'd33
`define CREG_ASHIFT_S2 16'd34
`define CREG_ASHIFT_S3 16'd35
`define CREG_ASHIFT_SI 16'd36
`define CREG_TS_FREQ_H 16'd37
`define CREG_TS_FREQ_L 16'd38
`define CREG_TS_PHASE 16'd39
`define CREG_TS_CW_A 16'd40
`define CREG_TS_CW_B 16'd41
`define CREG_TS_NOISE_A 16'd42
`define CREG_TS_NOISE_B 16'd43
`define CREG_CALPHASE 16'd44
`define CREG_BLANKSEL 16'd48
`define CREG_BLANKPER 16'd49
`define CREG_OVFADC_THRESH 16'd50
`define CREG_OVFADC_DWELL 16'd51
`define CREG_CALSEL 16'd52
`define CREG_CALCTL 16'd54
`define CREG_CALON 16'd55
`define CREG_CALOFF 16'd56
`define CREG_DLO 16'd57
`define CREG_DLO_PHASE 16'd58

// HR mode registers
//
`define CREG_HR_MODE 16'd59
`define CREG_HR_DEC 16'd60
`define CREG_HR_SHIFT 16'd61
`define CREG_HR_OFFSET 16'd62
`define CREG_HR_LPF 16'd63
`define CREG_DLO_DWELL 16'd64
`define CREG_DLO_INC 16'd65

// Base address for 8k byte sections of PFB FIR filter coefficient memory
//
`define CREG_PFB0 16'h8000
`define CREG_PFB1 16'ha000
`define CREG_PFB2 16'hc000
`define CREG_PFB3 16'he000

// In HR mode, address for 4 1K registers blocks for decimating LPF
// filter coefficients.
//
`define CREG_LPF_C0 16'h4000
`define CREG_LPF_C1 16'h4400
`define CREG_LPF_C2 16'h4800
`define CREG_LPF_C3 16'h4c00

// A few different chip builds, only one of these should be
// defined, this might actually be defined by a parameter to
// simulation or the xilinx toolchain.
//
// This is the 'normal' chip. Full stokes calculation and 32-bit
// accumulation.
//
// `define N_CHIPA

// This is does not calculate the two polarization stokes parameters
// (U&V) but does higher resolution accumulation of power.
//
// `define N_CHIPB

// This is a big chip, requires a 2VP70, does high resolution
// accumulation of all four stokes parameters.
//
// `define N_CHIPC


//
// Datapath widths
//


// Maximum transform length, jfft needs to be passed the same
// parameter or you get a weird unbalanced system. This sets the
// size of memories in the accumulators and the polarity alignment
// delay after the PFB.
//
`define N_MAX 8192

// Width of FFT and output of PFB, if this is something other than
// 18, there is some virtex-2 specific code for stokes calculation that
// needs to be fix manually for the multiplier instances. N_PFB also
// needs to match width of PFB in jfft build of PFB code.
//
`define N_PFB 18
`define N_SFT (`N_PFB+7)
`define N_ASFT (`N_ACC+15)

// Bits kept from multipler in stokes and power calculations
// The virtex multipliers are 18x18=36 bits, but the multiplies
// are 1.17 x 1.17 = 1.34, the high bit of the multiplier is
// dropped leaving a 35-bit result. If this value is changed from
// 35-bits the virtex2 multiplier instances need to be fixed up.
//
`define N_MUL 35


// Special defines for different chip configurations.
//
// N_ACC is the width of the accumulators. N_ACC needs to be at least
// 32-bits.
// N_FULL_STOKES is a defined that enables calculation and accumulation
// of all four stokes parameters. If not defined then only
// power is calculated and integrated for the two polarities.
// N_BIGACC must be defined if N_ACC is greater than N_MUL. It must
// not be defined if N_ACC is less than or equal to N_MUL. This
// makes up for some crazy stuff with verilog defines.
// N_HR turns on high resolution mode, puts a mixer in front of the
// pfb and adds a variable decimation low pass filter before pfb.
//
`ifdef N_CHIPA
`define N_FULL_STOKES
`define N_ACC 32
`endif

`ifdef N_CHIPB
`define N_BIGACC
`define N_ACC 40
`endif

`ifdef N_CHIPC
`define N_FULL_STOKES
`define N_BIGACC
`define N_ACC 40
`endif

`ifdef N_CHIPD
`define N_FULL_STOKES
`define N_BIGACC
`define N_ACC 40
`define N_HR
`endif