Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/sp/src/adcin.v Дата изменения: Thu Jun 26 04:27:55 2008 Дата индексирования: Sat Sep 6 19:50:35 2008 Кодировка: Поисковые слова: релятивистское движение

// Jeff Mock
// 2030 Gough St.
// San Francisco, CA 94109
// jeff@mock.com
//
// Copyright 2005,2006
//
// $URL: https://www.mock.com/svn/pdev/trunk/gx/sp/src/adcin.v $
// $Id: adcin.v 913 2007-02-24 01:09:40Z jeff $

// ADC inputs, test signal, signal conditioning
//

module adcin (
ck,
reset,
obs_start,
creg_ts_freq,
creg_ts_phase,
creg_ts_cw_a,
creg_ts_cw_b,
creg_ts_noise_a,
creg_ts_noise_b,

adc0_dat,
adc0_ovl,
adc1_dat,
adc1_ovl,
adc2_dat,
adc2_ovl,
adc3_dat,
adc3_ovl,

ar,
ai,
br,
bi,

frame_write,
acc_frame,
ovf_adc,
ovf_adc_any,

creg_arsel,
creg_aisel,
creg_brsel,
creg_bisel,
creg_arneg,
creg_aineg,
creg_brneg,
creg_bineg
);
input ck;
input reset;
input obs_start;
input [31:0] creg_ts_freq;
input [15:0] creg_ts_phase;
input [15:0] creg_ts_cw_a;
input [15:0] creg_ts_cw_b;
input [15:0] creg_ts_noise_a;
input [15:0] creg_ts_noise_b;

// ADC input pads
//
input [`N_ADC-1:0] adc0_dat;
input adc0_ovl;
input [`N_ADC-1:0] adc1_dat;
input adc1_ovl;
input [`N_ADC-1:0] adc2_dat;
input adc2_ovl;
input [`N_ADC-1:0] adc3_dat;
input adc3_ovl;

output [`N_ADC-1:0] ar;
output [`N_ADC-1:0] ai;
output [`N_ADC-1:0] br;
output [`N_ADC-1:0] bi;

input frame_write;
input acc_frame;
output [3:0] ovf_adc;
output ovf_adc_any;

input [2:0] creg_arsel;
input [2:0] creg_aisel;
input [2:0] creg_brsel;
input [2:0] creg_bisel;
input creg_arneg;
input creg_aineg;
input creg_brneg;
input creg_bineg;

// Test signal generator for digital diags
//
wire [`N_ADC-1:0] ts_ar;
wire [`N_ADC-1:0] ts_ai;
wire [`N_ADC-1:0] ts_br;
wire [`N_ADC-1:0] ts_bi;
testsig testsig (
.ck ( ck ),
.reset ( reset ),

.obs_start ( obs_start ),
.creg_ts_freq ( creg_ts_freq ),
.creg_ts_phase ( creg_ts_phase ),
.creg_ts_cw_a ( creg_ts_cw_a ),
.creg_ts_cw_b ( creg_ts_cw_b ),
.creg_ts_noise_a ( creg_ts_noise_a ),
.creg_ts_noise_b ( creg_ts_noise_b ),

.ts_ar ( ts_ar ),
.ts_ai ( ts_ai ),
.ts_br ( ts_br ),
.ts_bi ( ts_bi )
);

// Mux to select ar,ar,br,bi, from four ADC inputs
//
reg [`N_ADC-1:0] ar_in;
reg ar_ovl_in;
reg [`N_ADC-1:0] ai_in;
reg ai_ovl_in;
reg [`N_ADC-1:0] br_in;
reg br_ovl_in;
reg [`N_ADC-1:0] bi_in;
reg bi_ovl_in;
always @(posedge ck)
case (creg_arsel[1:0])
2'd0: begin
ar_in <= adc0_dat;
ar_ovl_in <= adc0_ovl;
end
2'd1: begin
ar_in <= adc1_dat;
ar_ovl_in <= adc1_ovl;
end
2'd2: begin
ar_in <= adc2_dat;
ar_ovl_in <= adc2_ovl;
end
2'd3: begin
ar_in <= adc3_dat;
ar_ovl_in <= adc3_ovl;
end
endcase

always @(posedge ck)
case (creg_aisel[1:0])
2'd0: begin
ai_in <= adc0_dat;
ai_ovl_in <= adc0_ovl;
end
2'd1: begin
ai_in <= adc1_dat;
ai_ovl_in <= adc1_ovl;
end
2'd2: begin
ai_in <= adc2_dat;
ai_ovl_in <= adc2_ovl;
end
2'd3: begin
ai_in <= adc3_dat;
ai_ovl_in <= adc3_ovl;
end
endcase

always @(posedge ck)
case (creg_brsel[1:0])
2'd0: begin
br_in <= adc0_dat;
br_ovl_in <= adc0_ovl;
end
2'd1: begin
br_in <= adc1_dat;
br_ovl_in <= adc1_ovl;
end
2'd2: begin
br_in <= adc2_dat;
br_ovl_in <= adc2_ovl;
end
2'd3: begin
br_in <= adc3_dat;
br_ovl_in <= adc3_ovl;
end
endcase

always @(posedge ck)
case (creg_bisel[1:0])
2'd0: begin
bi_in <= adc0_dat;
bi_ovl_in <= adc0_ovl;
end
2'd1: begin
bi_in <= adc1_dat;
bi_ovl_in <= adc1_ovl;
end
2'd2: begin
bi_in <= adc2_dat;
bi_ovl_in <= adc2_ovl;
end
2'd3: begin
bi_in <= adc3_dat;
bi_ovl_in <= adc3_ovl;
end
endcase

// Independently negate each ADC according to
// control bit.
//
reg [`N_ADC-1:0] ar_neg;
reg [`N_ADC-1:0] ai_neg;
reg [`N_ADC-1:0] br_neg;
reg [`N_ADC-1:0] bi_neg;
reg ar_ovl_neg;
reg ai_ovl_neg;
reg br_ovl_neg;
reg bi_ovl_neg;
always @(posedge ck) begin
ar_neg <= creg_arneg ? -ar_in : ar_in;
ai_neg <= creg_aineg ? -ai_in : ai_in;
br_neg <= creg_brneg ? -br_in : br_in;
bi_neg <= creg_bineg ? -bi_in : bi_in;
ar_ovl_neg <= ar_ovl_in;
ai_ovl_neg <= ai_ovl_in;
br_ovl_neg <= br_ovl_in;
bi_ovl_neg <= bi_ovl_in;
end

// Independently add offset to ADC values
// A selector of 5 zeros an input
//
reg [`N_ADC-1:0] ar;
reg [`N_ADC-1:0] ai;
reg [`N_ADC-1:0] br;
reg [`N_ADC-1:0] bi;
reg ar_ovf;
reg ai_ovf;
reg br_ovf;
reg bi_ovf;
always @(posedge ck) begin
ar <= creg_arsel[2] ? (creg_arsel[0] ? `N_ADC'b0 : ts_ar) : ar_neg;
ai <= creg_aisel[2] ? (creg_aisel[0] ? `N_ADC'b0 : ts_ai) : ai_neg;
br <= creg_brsel[2] ? (creg_brsel[0] ? `N_ADC'b0 : ts_br) : br_neg;
bi <= creg_bisel[2] ? (creg_bisel[0] ? `N_ADC'b0 : ts_bi) : bi_neg;
ar_ovf <= ~creg_arsel[2] & ar_ovl_neg;
ai_ovf <= ~creg_aisel[2] & ai_ovl_neg;
br_ovf <= ~creg_brsel[2] & br_ovl_neg;
bi_ovf <= ~creg_bisel[2] & bi_ovl_neg;
end

// Count ADC overflows
//
ovfcnt ovf (
.ck ( ck ),
.reset ( reset ),
.ovf ( (ar_ovf | ai_ovf | br_ovf | bi_ovf) &
frame_write ),
.acc_frame ( acc_frame ),
.ovf_status ( ovf_adc )
);

reg ovf_adc_any;
always @(posedge ck)
ovf_adc_any <= ar_ovf | ai_ovf | br_ovf | bi_ovf;
endmodule