Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/jfft/src/test.v Дата изменения: Thu Jun 26 04:28:48 2008 Дата индексирования: Sat Sep 6 19:54:13 2008 Кодировка: Поисковые слова: rigel

//
// Jeff Mock
// 2030 Gough
// San Francisco, CA 94109
// jeff@mock.com
// (c) 2004
//

// $URL: https://www.mock.com/svn/pdev/trunk/gx/jfft/src/test.v $
// $Id: test.v 162 2006-06-11 18:23:58Z jeff $

module test (
ck,
`ifdef CERATE
ce,
`endif
`ifdef VARLEN
diag_mode,
diag_we,
diag_addr,
diag_sel,
diag_data,
diag_data_rd,
`endif
reset,
sync_i,
sync_o,

a_re,
a_im,
b_re,
b_im,

ovf,
x_re,
x_im,
y_re,
y_im
);
parameter width = `WIDTH;
parameter iwidth = `IWIDTH;

input ck;

`ifdef CERATE
input ce;
`else
wire ce;
assign ce = 1'b1;
`endif

`ifdef VARLEN
output diag_mode;
output diag_we;
output [12:0] diag_addr;
output [1:0] diag_sel;
output [17:0] diag_data;
input [17:0] diag_data_rd;
`endif

output reset;
output sync_i;
input sync_o;

output [iwidth-1:0] a_re;
output [iwidth-1:0] a_im;
output [iwidth-1:0] b_re;
output [iwidth-1:0] b_im;

input ovf;
input [width-1:0] x_re;
input [width-1:0] x_im;
input [width-1:0] y_re;
input [width-1:0] y_im;

// Cycle counter
//
integer cycle;
initial begin
cycle = 0;
forever @(posedge ck) begin
if (ce) begin
cycle = cycle + 1;
if (cycle == 100000) begin
$display("Runaway simulation.");
$finish;
end
`ifdef DEBUG
if ((cycle%100) == 0)
$display ("Cycle %d", cycle);
`endif
end
end
end

// Reset the hardware
//
// Generate sync pulse to FFT. The first sample of signal
// should appear on the second sync_i pulse.
//
reg sync_i;
reg reset;
reg run;
reg coeff_loaded;
integer len;
integer scnt;
initial begin
sync_i = 1'b0;
reset = 1'b0;
run = 1'b0;
len = `LENGTH-30;
scnt = 0;
coeff_loaded = 1'b1;
repeat (20)
@(posedge ck);
reset = 1'b1;
repeat (4)
@(posedge ck);
reset = 1'b0;
repeat (10)
@(posedge ck);
while (!coeff_loaded)
@(posedge ck);
forever begin
@(posedge ck) begin
if (ce) begin
if (len == 0)
sync_i = 1'b0;
if (len == `LENGTH-1) begin
sync_i = 1'b1;
len = 0;
end else
len = len+1;
end
end
end
end

// First frame is always dummy frame
//
always @(posedge ck)
if (ce & sync_i) begin
scnt = scnt + 1;
if (scnt > 1)
run = 1'b1;
end

`ifdef PFB_COEFF_LOAD
// Load coefficient tables for PFB FIR if we're doing a behavioral
// sim.
//
initial begin
#10
coeff_loaded = 1'b0;
$readmemh("gen/coeff0", top.fft.pfb.c0.coeff_p_mem);
$readmemh("gen/coeff1", top.fft.pfb.c1.coeff_p_mem);
$readmemh("gen/coeff2", top.fft.pfb.c2.coeff_p_mem);
$readmemh("gen/coeff3", top.fft.pfb.c3.coeff_p_mem);
coeff_loaded = 1'b1;
$display("Direct loading of PFB coefficients");
end
`endif

`ifdef VARLEN
reg diag_mode;
reg diag_we;
reg [12:0] diag_addr;
reg [1:0] diag_sel;
reg [17:0] diag_data;
initial begin
diag_mode = 1'b0;
diag_we = 1'b0;
end
`endif

`ifdef PFB_COEFF_WRITE
reg [17:0] tmem [0:8191];
integer addr;

// Write coefficients through diagnostic interface, works for virtex2
// implementation or gate level
initial begin
$display("Load PFB coefficients through diag interface");
@ (negedge reset);
coeff_loaded = 1'b0;

repeat (10)
@ (posedge ck);
diag_mode = 1'b1;

diag_sel = 2'd0;
$readmemh("gen/coeff0", tmem);
addr = 0;
while (addr < `LENGTH+10) begin
diag_addr = addr;
diag_we = 1'b1;
diag_data = tmem[addr];
@ (posedge ck);
addr = addr + 1;
end
diag_we = 1'b0;
@ (posedge ck);

diag_sel = 2'd1;
$readmemh("gen/coeff1", tmem);
addr = 0;
while (addr < `LENGTH+10) begin
diag_addr = addr;
diag_we = 1'b1;
diag_data = tmem[addr];
@ (posedge ck);
addr = addr + 1;
end
diag_we = 1'b0;
@ (posedge ck);

diag_sel = 2'd2;
$readmemh("gen/coeff2", tmem);
addr = 0;
while (addr < `LENGTH+10) begin
diag_addr = addr;
diag_we = 1'b1;
diag_data = tmem[addr];
@ (posedge ck);
addr = addr + 1;
end
diag_we = 1'b0;
@ (posedge ck);

diag_sel = 2'd3;
$readmemh("gen/coeff3", tmem);
addr = 0;
while (addr < `LENGTH+10) begin
diag_addr = addr;
diag_we = 1'b1;
diag_data = tmem[addr];
@ (posedge ck);
addr = addr + 1;
end
diag_we = 1'b0;
@ (posedge ck);
$display("Coefficients loaded.");

repeat (10)
@ (posedge ck);
diag_mode = 1'b0;
repeat (10)
@ (posedge ck);
coeff_loaded = 1'b1;
end
`endif

// Send signal file to FFT
//
reg [iwidth-1:0] sigmem1[0:2*`FRAMES*`LENGTH - 1];
reg [iwidth-1:0] sigmem2[0:2*`FRAMES*`LENGTH - 1];
reg [iwidth-1:0] a_re;
reg [iwidth-1:0] a_im;
reg [iwidth-1:0] b_re;
reg [iwidth-1:0] b_im;
integer idx;

integer s1;
integer s2;

`ifdef SIG1
`else
`define SIG1 "sig1.mem"
`endif

`ifdef SIG2
`else
`define SIG2 "sig2.mem"
`endif

`ifdef FFTOUT
`else
`define FFTOUT "fft.out"
`endif

initial begin
idx = 0;
$readmemh(`SIG1, sigmem1);
$readmemh(`SIG2, sigmem2);
end
always @(posedge ck) begin
if (ce) begin
if ($test$plusargs("p1zero") || !run) begin
a_re = 0;
a_im = 0;
end else begin
if ($test$plusargs("p1step")) begin
if (cycle < 450) begin
a_re = 0;
a_im = 0;
end else begin
a_re = 100;
a_im = 100;
end
end else if ($test$plusargs("p1noise")) begin
s1 = $random(s1);
a_re = s1[iwidth-1:0];
s1 = $random(s1);
a_im = s1[iwidth-1:0];
end else begin
if (idx >= 2*`FRAMES*`LENGTH) begin
a_re = 0; // { `IWIDTH {1'bx} };
a_im = 0; // { `IWIDTH {1'bx} };
end else begin
a_re = sigmem1[idx];
a_im = sigmem1[idx+1];
end
end
end

if ($test$plusargs("p2zero") || !run) begin
b_re = 0;
b_im = 0;
end else begin
if ($test$plusargs("p2step")) begin
if (cycle < 450) begin
b_re = 0;
b_im = 0;
end else begin
b_re = 100;
b_im = 100;
end
end else if ($test$plusargs("p2noise")) begin
s2 = $random(s2);
b_re = s2[iwidth-1:0];
s2 = $random(s2);
b_im = s2[iwidth-1:0];
end else begin
if (idx >= 2*`FRAMES*`LENGTH) begin
b_re = 0; // { `IWIDTH {1'bx} };
b_im = 0; // { `IWIDTH {1'bx} };
end else begin
b_re = sigmem2[idx];
b_im = sigmem2[idx+1];
end
end
end
if (run)
idx = idx+2;
end
end

// Capture valid frames of reordered FFT output and write
// to file.
//
integer socnt;
integer fcnt;
integer fbin;
integer fd;
initial begin
fd = $fopen(`FFTOUT);
socnt = 0;
fcnt = 0;
end
always @(posedge ck) begin
if (ce) begin
if (sync_o) begin
socnt = socnt + 1;
fbin = -`LENGTH / 2;
end

if (socnt > 1) begin
if (sync_o) begin
fcnt = fcnt + 1;
$fdisplay(fd,"");
end
$fdisplay(fd, "%d %x %x %x %x %b", fbin,
x_re, x_im, y_re, y_im, ovf);
if (fcnt == `FRAMES && fbin == `LENGTH/2-1) begin
// $display("Normal termination after %d frames", `FRAMES);
$fclose(fd);
// repeat (500)
// @ (posedge ck);
$finish;
end
end
fbin = fbin + 1;
end
end
endmodule