Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/pdev/fpga/gx/jfft/pdev/rtl/xfft_stage_9.v Дата изменения: Thu Jun 26 04:28:51 2008 Дата индексирования: Sat Sep 6 20:38:18 2008 Кодировка: Поисковые слова: morning star

// This is a template for all stages except 0 and 1. mkjfft_stage_n
// makes some substitutions and generates verilog
// for other stages.
//
// Stage number 9
// module pipeline delays 517
// commutator delay 512
//
// phase bits 10
// phase bits minus 1 9
// phase bits minus 2 8
// Name of twiddle module 8192_512_8
// Programmable downshift with rounding
//
// Total delay of module (517).
//
// Generated by mkjfft_stage
//
module xfft_stage_9 (
ck,
reset,
bypassb,
pshift,
sync_i,
sync_o,

a_re,
a_im,
b_re,
b_im,

ovf,
x_re,
x_im,
y_re,
y_im
);
parameter width=18;

input ck;
input reset;
input bypassb;
input pshift;
input sync_i;
output sync_o;

input [width-1:0] a_re;
input [width-1:0] a_im;
input [width-1:0] b_re;
input [width-1:0] b_im;

output ovf;
output [width-1:0] x_re;
output [width-1:0] x_im;
output [width-1:0] y_re;
output [width-1:0] y_im;

wire [width-1:0] ca_re;
wire [width-1:0] ca_im;
wire [width-1:0] cb_re;
wire [width-1:0] cb_im;

reg [width-1:0] x_re;
reg [width-1:0] x_im;
reg [width-1:0] y_re;
reg [width-1:0] y_im;
reg sync_o;

// reg reset_d;
// always @(posedge ck)
// reset_d <= reset;

// Delay sync output by appropropriate pipeline stages
//
wire sync_op;
xfft_sync_517 pdel (
.ck ( ck ),
.reset ( reset ),
.i ( sync_i ),
.o ( sync_op )
);

reg [9:0] phase, phase_n;
reg [9:0] phasep2, phasep2_n;
reg [3:0] ph_drv;
always @(sync_i or reset or phase or phasep2) begin
if (sync_i | reset) begin
phase_n = 10'd0;
phasep2_n = 10'd2;
end else begin
phase_n = phase + 10'd1;
phasep2_n = phasep2 + 10'd1;
end
end
always @(posedge ck) begin
phase <= phase_n;
phasep2 <= phasep2_n;
ph_drv[0] <= phase_n[9];
ph_drv[1] <= phase_n[9];
ph_drv[2] <= phase_n[9];
ph_drv[3] <= phase_n[9];
end

// Add 1 to input for rounding before downshift
//
wire [width-1:0] as_re;
wire [width-1:0] as_im;
wire [width-1:0] bs_re;
wire [width-1:0] bs_im;
assign as_re = a_re + 18'd1;
assign as_im = a_im + 18'd1;
assign bs_re = b_re + 18'd1;
assign bs_im = b_im + 18'd1;

reg [width-1:0] ax_re;
reg [width-1:0] ax_im;
reg [width-1:0] bx_re;
reg [width-1:0] bx_im;
always @(posedge ck) begin
ax_re <= pshift ? { as_re[width-1], as_re[width-1:1] } : a_re;
ax_im <= pshift ? { as_im[width-1], as_im[width-1:1] } : a_im;
bx_re <= pshift ? { bs_re[width-1], bs_re[width-1:1] } : b_re;
bx_im <= pshift ? { bs_im[width-1], bs_im[width-1:1] } : b_im;
end

// Delay B side by 512 clocks
//
wire [width-1:0] b_re_del;
wire [width-1:0] b_im_del;
xfft_delay_512 del_b (
.ck ( ck ),
.reset ( reset ),
.in_re ( bx_re ),
.in_im ( bx_im ),
.out_re ( b_re_del ),
.out_im ( b_im_del )
);

// A/B commutator
//
assign ca_re = ph_drv[0] ? b_re_del : ax_re;
assign ca_im = ph_drv[1] ? b_im_del : ax_im;
assign cb_re = ph_drv[2] ? ax_re : b_re_del;
assign cb_im = ph_drv[3] ? ax_im : b_im_del;

// Delay A side by 512 clocks
//
wire [width-1:0] ca_re_del;
wire [width-1:0] ca_im_del;
xfft_delay_512 del_a (
.ck ( ck ),
.reset ( reset ),
.in_re ( ca_re ),
.in_im ( ca_im ),
.out_re ( ca_re_del ),
.out_im ( ca_im_del )
);

// The butterfly, a single pipeline delay
//
wire [width-1:0] x_bf_re;
wire [width-1:0] x_bf_im;
wire [width-1:0] y_bf_re;
wire [width-1:0] y_bf_im;
xfft_bf bf (
.ck ( ck ),
.a_re ( ca_re_del ),
.a_im ( ca_im_del ),
.b_re ( cb_re ),
.b_im ( cb_im ),

.ovf ( ovf ),
.x_re ( x_bf_re ),
.x_im ( x_bf_im ),
.y_re ( y_bf_re ),
.y_im ( y_bf_im )
);

wire [width-1:0] tw_re;
wire [width-1:0] tw_im;
xfft_twiddle_8192_512_8 tw (
.ck ( ck ),
.addr ( phasep2[8:0] ),
.tw_re ( tw_re ),
.tw_im ( tw_im )
);

// Multiply Y portion by twiddle factor
//
wire [width-1:0] y_tw_re;
wire [width-1:0] y_tw_im;
xfft_cm cm (
.ck ( ck ),
.a_re ( y_bf_re ),
.a_im ( y_bf_im ),
.b_re ( tw_re ),
.b_im ( tw_im ),

.x_re ( y_tw_re ),
.x_im ( y_tw_im )
);

// Delay X portion of buterfly to match twiddle multiplication
wire [width-1:0] x_del_re;
wire [width-1:0] x_del_im;
xfft_delay_3 del_cm (
.ck ( ck ),
.reset ( reset ),
.in_re ( x_bf_re ),
.in_im ( x_bf_im ),
.out_re ( x_del_re ),
.out_im ( x_del_im )
);


// Bypass stage with a single pipeline delay if bypass
// input is asserted. With bypass feature enabled, each
// FFT stage is one additional pipeline stage when enabled.
//
reg bypass_d1;
always @(posedge ck) begin
bypass_d1 <= ~bypassb;
x_re <= bypass_d1 ? a_re : x_del_re;
x_im <= bypass_d1 ? a_im : x_del_im;
y_re <= bypass_d1 ? b_re : y_tw_re;
y_im <= bypass_d1 ? b_im : y_tw_im;
sync_o <= bypass_d1 ? sync_i : sync_op;
end
endmodule