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EALFA / PALFA BASEBAND MIXERS
Theory of operation & Circuit Description
Introduction: The purpose of this subsystem is to convert a 300-MHz segment of IF spectrum originating in the ALFA receivers to quadrature baseband signals for subsequent A/D conversion. The design is targeted at an input spectrum spanning 100 to 400 MHz. However, the maximum sample rate of the A/D converters is only about 200 MHz, so it is necessary to split the input band into two sub-bands, each 150 MHz wide, so that the highest frequency component in any of the outputs is comfortably less than 100 MHz (75 MHz in reality). The nominal LO frequencies for this subsystem are 175 MHz for the "IF low band" and 325 MHz for the "IF high band". Note that there is some potential for confusion about "low band" versus "high band". The IF low and high bands are reversed from the RF or "sky" low and high bands because the ALFA system's 1st LO frequency is higher than the top of the RF band, resulting in a frequency order inversion. In this document the terms "low band" and "high band" will always refer to the IF frequency domain unless otherwise noted. Note that the ALFA system includes a total of fourteen receiver channels to accommodate two polarizations for each of seven "pixels". This baseband mixer system will also comprise fourteen channels, partitioned as one channel per board. The two boards for a pixel's two polarizations will be mounted in a common 1RU box. Seven pixels, seven boxes. Each box will provide two well-isolated sets of outputs, comprising 16 individual signals, derived from two sets * two sub-bands * two polarizations * two "phases" (I & Q). This discussion will cover only a single channel, which does include both sub-bands. And the discussion will concentrate on only one sub-band, because the other sub-band is virtually identical except for filter passband limits and a different model number for the quadrature hybrid used as the LO splitter. Notes regarding the figures: For the following please refer to Figure 1 (block diagram) and Figures 2 through 17 (ORCAD diagrams). For most of the discussion you will be able to follow along using either Figure 1 or Figure 2, and references to other figures will mostly be optional pointers to more detailed schematics for the curious. In some cases, however, references to the underlying schematics will be important; the relevant figures will be emphatically pointed out in such cases. The reference designators used in the block diagram correspond to those used in the actual ORCAD schematics. The block diagram also includes information about anticipated maximum signal levels.


The component references made in the course of the discussion will generally be limited to those for the low band path (and for the EALFA `I' channel sub-paths beyond the demodulator stage), and schematics are only provided within the same constraint. With the exception of the different quadrature hybrid in the high band demodulator block, the schematics for the corresponding blocks in other paths are identical except for different reference designators. Signal Flow Description: The full bandwidth input signal is applied to J3, whereupon it is split into two identical signals by H1-1 (Figure 3). One of these signals is destined to be filtered for the low sub-band (100-250 MHz, hereafter referred to simply as the low band), and the other is filtered for the high band (250-400 MHz). Note that in the present design only lowpass filters are used, for two reasons: flexibility and economy. It was thought that some users could benefit from the ability to slightly modify the choice of IF frequencies, and using full bandpass filtering would restrict this freedom. The ECB design does, however, include pads for the inclusion of appropriate highpass filters in one or both paths as well, in the event that unforeseen problems arise from the exclusive use of lowpass filters. Now let's pursue the signal through the low band. Following the low band filter (LPF1), the signal passes through a programmable step attenuator (H2-1, Figure 4) which gives 1 dB granularity over an attenuation range of about 30 db. Note that the matter of what signal levels to push through this system is fraught with compromise. A high signal level reduces the relative contribution of noise, ingress, and A/D spurs, at the price of reduced dynamic range. That is, the system will be more susceptible to development of intermodulation products and will be driven deeper into saturation by the highamplitude radar pulses that inhabit portions of the L-band. Operating with a low signal level, on the other hand, leaves the user with increased corruption from the inevitable essentially fixedamplitude disturbances such as A/D spurs, ingress of various signals due to imperfect shielding, etc. The purpose for providing user control of the step attenuator settings is to allow the user to select the best compromise for his/her particular application. It is anticipated that with experience, a reasonably-fixed set of good attenuator settings for each general observing application will emerge. Next the signal passes through two gain stages (H3-1 & H3-3, Figures 5 & 6) with an intermediate fixed attenuator (U5). Unfortunately the input signal frequently includes the highamplitude radar pulses alluded to earlier, and the intermediate attenuators seen at several places in this design are chosen to avoid the risk of outright burnout of subsequent stages. It may be instructive to review the signal level captions on Figure 1. This architecture of alternating gain and attenuation stages also provides the benefits of better reverse isolation through the path as well as avoiding the risk of instabilities or oscillation if some of the amplifiers are not as unconditionally stable as the manufacturer claims. Following the second gain stage, the low band signal is once again split into two paths, by H1-2 (Figure 3). The primary path takes the signal through attenuator U4 to the quadrature mixer block H4-1 (now definitely check out Figure 8). We'll get back to the secondary path later.


Within the mixer block the signal is split yet another time by H1, to the two diode ring mixers U40 & U45. These mixers are also provided LO signals which are in quadrature phase, having been passed through amplifier U43 and the quadrature hybrid U42. The two LO signals also pass through attenuators U41 & U44 on their way to the mixers in order to provide better terminations to the outputs of U42 in order to obtain the best possible quadrature phase accuracy (we hope!). The in-phase (I) and quadrature-phase (Q) mixer outputs each pass through an attenuator (U3 for `I', U12 for `Q') to provide good broadband terminations to the mixers' IF ports, then to 75 MHz lowpass filters LPF2 and LPF3. It is these filters that are primarily responsible for blocking undesired high frequency energy that would cause aliasing in the A/D converters, which will normally be operated at a sample rate of 170 MHz. Note that the I & Q signals need flat response down to nearly zero frequency for the remainder of the signal path to the A/D converters- this factor will impact the design of subsequent stages. Next, the band-limited I & Q signals are each split into two paths for the two isolated outputs, using resistive splitters for the sake of their DC frequency response. Resistive splitters, however, provide very poor isolation between their outputs; therefore the remainder of the path includes multiple amplifiers (H5-1 & H6-1) along with attenuators U1 & U2 in order to provide good reverse isolation. In the event that one output of each pair is left unterminated, negligible impact occurs to the other output. Note that the amplifiers H5-1 & H6-1 (Figures 9 & 10, respectively) deviate from standard practice in that the inductors usually found in the bias networks are omitted, making it practical to obtain reasonably flat frequency response down to very low frequencies. The price paid is slightly reduced values for the gain and for the maximum output level from the amplifiers. Now let's carry on with the previously-deferred discussion of the secondary signal path following the splitter H1-2. The purpose of this path is to provide an analog square-law-detected output for convenience in setting the step attenuator and for quick verification that reasonable signal levels are present. The signal passes through attenuator U8, amplifier H3-5 (Figure 5), and attenuator U9 on its way to the detector module H7-1 (now see Figure 11). The detector module includes a simple diode detector (R44, D1, & C49) followed by gain stage U47A and inverter stage U47B. This detector is operated in the square law regime for reasonable system noise levels, but will generally be pushed beyond the square law regime by the radar pulses. Together, these stages provide a very low DC drift differential output with a nominal sensitivity of 100 mV / µW (based on datasheet specifications for the detector diode). The detector's differential output is brought to pin jacks on the front panel; additionally the detector's output may read back via the attenuator control interface (H8, please see Figure 12). The high-band signal path is identical to that of the low-band, with two exceptions: · The lowpass filter cutoff is nominally 400 MHz instead of 250 MHz. · The LO frequency is nominally 325 MHz instead of 175 MHz. · The quadrature hybrid used in the demodulator block is a different model for the higher LO frequency.


EALFA/PALFA BASEBAND MIXER

-37.5 dBm (calc sys noise in 75 MHz) -15 dBm PEP (est sat'd output) -119.5 dBm / Hz (calc sys noise density) (all at min atten) -18.5 dBm (calc sys noise in 150 MHz) 15 dBm PEP (est sat'd output) -100.5 dBm / Hz (calc sys noise density) (all at min atten) -3.5 dBm (calc sys noise in 150 MHz) 20 dBm PEP (est sat'd output) -85.5 dBm / Hz (calc sys noise density) (all at min atten)

-17 dBm (calc sys noise in 75 MHz) +5.5 dBm PEP (est sat'd output) -99 dBm / Hz (calc sys noise density) (all at min atten) -11 dBm (calc sys noise in 75 MHz) +11.5 dBm PEP (est sat'd output) -93 dBm / Hz (calc sys noise density) (all at min atten) -17 dBm (calc sys noise in 75 MHz) +5.5 dBm PEP (est sat'd output) -99 dBm / Hz (calc sys noise density) (all at min atten)

-30 dBm (meas sys noise in 300 MHz) +10 dBm PEP (est radar peaks) -115 dBm / Hz (calc sys noise density) -39 dBm (calc sys noise in 150 MHz) +4 dBm PEP (est radar peaks) -121 dBm / Hz (calc sys noise density)

-34 dBm (calc sys noise in 300 MHz) +6 dBm PEP (est radar peaks) -119 dBm / Hz (calc sys noise density)

-22.5 dBm (calc sys noise in 75 MHz) 0 dBm PEP (est sat'd output) -104.5 dBm / Hz (calc sys noise density) (all at min atten)
20.5 dB

-40.5 dBm (calc sys noise in 150 MHz) +2.5 dBm PEP (est radar peaks) -122.5 dBm / Hz (calc sys noise density) (all at min atten)

-11.5 dBm (calc sys noise in 150 MHz) 12 dBm PEP (est sat'd output) -93.5 dBm / Hz (calc sys noise density) (all at min atten) Gain to each output is -11 db
8 dB I out

9 dB

15 dB ERA-2

6 dB

LPF (2x) F_1dB >= 75 MHz F_20dB <= 85 MHz Matched within 1.5 deg DC-75 MHz LPF2 U3

ERA-3

J1

EALFA Low-band I out

R2

R1 R3

H5-1
20.5 dB ERA-3

U1
9 dB

H6-1
15 dB ERA-2

U2
6 dB

J2

PALFA Low-band I out

H1-1 (TCP-2-10) IF in (10-400 MHz) -30 dBm baseline noise level in 300 MHz BW. "IF Low Band" 100-250 MHz nominal "IF High Band" 250-400 MHz nominal J3

1.0 dB I.L.
250 MHz LPF (TO-8 pkg) Dummy Filter (TO-8 pkg)

Programmable RF Attenuator
Hittite HMC470LP3 1.5-32.5 db 5 bits

TCP-2-10
22 dB ERA-3 5 dB 20 dB ERA-5

4 dB IF inp

Quadr_demod_MCL Q out LO inp

H5-2 LPF3
20.5 dB ERA-3

U6
9 dB

H6-2
15 dB ERA-2

U7
6 dB

8 dB

J5

U4 H4-1 -4 dB H1-2 U8
12 dB 16 dB ERA-2

U12

EALFA Low-band Q out

Approx 1 dB I.L.

R5

R4 R6

H5-3
20.5 dB ERA-3

LPF1 (LTC-???) -4 dB

H2-1

H3-1

U5

U10
9 dB

H6-3
15 dB ERA-2

U11
6 dB

H3-3

J7

PALFA Low-band Q out

H3-5
15 dB

U9 -19.5 dBm (calc sys noise in 150 MHz) -2 dBm PEP (est sat'd level) (at min atten)

H5-4

U13

H6-4

U14

Low Band Sq Law Det Out

p/o J4

Low band SQ law DET H7-1

LO in (IF Low band) (Quadrature splitter freq range 150-300 MHz)

J6

175 MHz (nominal) -3 dBm Low Band Level
Attenuator Control Interface

Atten Control

J17

Ser In

Par Out

20.5 dB

9 dB

15 dB ERA-2

6 dB

H8

High Band Level
8 dB

LPF (2x) F_1dB >= 75 MHz F_20dB <= 85 MHz Matched within 1.5 deg DC-75 MHz LPF5

ERA-3

J9

EALFA High-band I out

R8

R7 R9

H5-5
20.5 dB ERA-3

U16
9 dB

H6-5
15 dB ERA-2

U17
6 dB

J10

PALFA High-band I out

U19 1.0 dB I.L.
400 MHz LPF (TO-8 pkg) Dummy Filter (TO-8 pkg)

H5-6 LPF6
20.5 dB ERA-3

U22
9 dB

H6-6
15 dB ERA-2

U23
6 dB

H2-2
Hittite HMC470LP3 1.5-32.5 db 5 bits

TCP-2-10
22 dB ERA-3 5 dB 20 dB ERA-5

4 dB IF inp

Quadr_demod_MCL Q out LO inp

8 dB

J12

U21 H4-2 -4 dB H1-3
12 dB 16 dB ERA-2

U26

EALFA High-band Q out

Approx 1 dB I.L.

R11

R10 R12

H5-7
20.5 dB ERA-3

U24
9 dB

H6-7
15 dB ERA-2

U25
6 dB

LPF4 (LTC-???)

Programmable RF Attenuator

H3-2

U20

H3-4

J13

PALFA High-band Q out

U18

H3-6
15 dB

U15

H5-8

U27

H6-8

U28

High Band Sq Law Det Out

p/o J4

High band DET H7-2

LO in (IF High band) (Quadrature splitter freq range 225-400 MHz)

J11

325 MHz (nominal) -3 dBm

FIGURE 1:

EALFA/PALFA BASEBAND MIXER BLOCK DIAGRAM (7th cut) using Ring Diode Demod instead This covers one polarization of 1 ALFA "pixel" (14 req'd)

Dana Whitlow 25 Oct 2007 TOO_EALFA_ANALOG_7d_FIG_1_rev1.fc7


5

4

3

2

1

DCBiasBBERA3_1

DCBiasBBERA2_1

R1 16.5 SM/C_0805 DCB_MIXERS +5VDCin DCB_ERA3LB LPF1 100-250MHz LARK_LTC_TO8-4 1 LPF fc 2 4 3 1 HPF1 (Place Holder) 100-250MHz LARK_LTC_TO8-4 HPF fc 2 4 +5VDCin 3 IFin IFout DCBias IFin IFout DCB_ERA5LB PORT1 U5 PAT-5 1 3 DCBias IFin IFout SUMPORT U8 PAT-12 H3-1 ERA-3 H3-3 ERA-5 H1-2 TCP-2-10 2 4 PORT2 H1-1 TCP-2-10 DCB_ERA2LB U9 PAT-15 SQLawOutSQLawOut+ 2 4 BandLevelMonitor H7-1 Square Law Detectors J4 CON10A 3M_2510-60XX-XX 10 8 6 4 2 J6 SMA H3-5 ERA-2 U12 PAT-8 1 31 IFin 1 3 R4 16.5 SM/C_0805 IFin LPF3 75MHz REACTEL_5LM LPF fc 3 4 5 2 DCBiasBBERA3_3 2 4 PORT2 1 3 U4 PAT-4 1 3 H4-1 Quadrature Diode-Ring Mixer DCBias IFin LOin Iout Qout U3 PAT-8 1 31 LPF2 75MHz REACTEL_5LM LPF fc 3 4 5 2

H5-1 DCBias BBin BBout

U1 PAT-9 1 3

H6-1 DCBias BBin BBout

U2 PAT-6 1 3 1 2 3 4 5

J1 SMA

R2 16.5 SM/C_0805 DCBiasBBERA3_2

2 4

Baseband ERA

Baseband ERA

DCBiasBBERA2_2
D

2 4

D

PORT1 J3 SMA 1 2 3 4 5 SUMPORT

R3 16.5 SM/C_0805

2 4

H5-2 DCBias BBin BBout

U6 PAT-9 1 3

H6-2 DCBias BBin BBout

U7 PAT-6 1 3 1 2 3 4 5

2 4

J2 SMA

AttCntrl[0..4] H2-1 Programmable Attenuator

2 4

Baseband ERA

Baseband ERA

DCBiasBBERA2_3

H5-3 DCBias BBin BBout

DCBias IFout

U10 PAT-9 1 3

H6-3 DCBias BBin BBout

U11 PAT-6 1 3 1 2 3 4 5

2 4

J5 SMA

R5 16.5 SM/C_0805 DCBiasBBERA3_4

2 4

Baseband ERA

Baseband ERA

DCBiasBBERA2_4

H8 +5VDCin +5VDCin LBAttCntrl[0..4] LBMon
C

2 4

LBAttCntrl[0..4]

9 7 5 3 1

LOin (Low Band)

1 2 3 4 5

R6 16.5 SM/C_0805

H5-4 DCBias BBin BBout

U13 PAT-9 1 3

H6-4 DCBias BBin BBout

U14 PAT-6 1 3 1 2 3 4 5

2 4

J7 SMA

C

2 4

Baseband ERA HBMon HBAttCntrl[0..4] Attenuator Control Interface HBAttCntrl[0..4]

Baseband ERA

Sq. Law Det. OUT

DCB_ERA2HB

BandLevelMonitor SQLawOutIFin SQLawOut+ H7-2 Square Law Detectors

U15 PAT-15 1 3

DCBias IFout IFin DCBiasBBERA3_5 H3-6 ERA-2 R7 16.5 SM/C_0805 DCBiasBBERA2_5

2 4

H5-5 DCBias BBin BBout

U16 PAT-9 1 3

H6-5 DCBias BBin BBout

U17 PAT-6 1 3 1 2 3 4 5

2 4

J9 SMA

DCB_ERA3HB LPF4 250-400MHz LARK_LTC_TO8-4 1
B

DCB_ERA5HB PORT1 U20 PAT-5 1 3

U18 PAT-12 1 3 DCB_MIXERS 2 4 SUMPORT U21 PAT-4 H4-2 Quadrature Diode-Ring Mixer 2 4 DCBias 3 IFin LOin Iout Qout U19 PAT-8 1 31 LPF5 75MHz REACTEL_5LM LPF fc 3 4 5 2 R8 16.5 SM/C_0805 DCBiasBBERA3_6

HPF2 (Place Holder) 100-250MHz LARK_LTC_TO8-4 1 HPF fc 2 4 AttCntrl[0..4] 3 IFin +5VDCin H2-2 Programmable Attenuator H3-2 ERA-3 IFout DCBias IFin IFout

2 4

Baseband ERA

Baseband ERA

DCBias IFin IFout

LPF fc 2 4

3

DCBiasBBERA2_6
B

+5VDCin 4 3 1 2

H3-4 ERA-5 H1-3 TCP-2-10

PORT2

1

R9 16.5 SM/C_0805

2 4

H5-6 DCBias BBin BBout

U22 PAT-9 1 3

H6-6 DCBias BBin BBout

U23 PAT-6 1 3 1 2 3 4 5

2 4

J10 SMA

2 4

2 4

Baseband ERA J11 SMA

Baseband ERA

LARK LTC FILTER BOTTOM VIEW

LOin (High Band)

1 2 3 4 5

DCBiasBBERA3_7

DCBiasBBERA2_7

R10 16.5 SM/C_0805 LPF6 75MHz REACTEL_5LM 31 LPF fc 3 4 5 2

H5-7 DCBias BBin BBout

U24 PAT-9 1 3

H6-7 DCBias BBin BBout

U25 PAT-6 1 3 1 2 3 4 5

2 4

J12 SMA

1 2 3 4 5 6 7 8 J14 CON8 MX_22-23-2081

+15VDCin +12VDCin +5VDCin -5VDCin +15VDCin +12VDCin +5VDCin -5VDCin J8 CON14A 3M_2514-60XX-XX 2 4 6 8 10 12 14 H9 +15VDCin +12VDCin +5VDCin -5VDCin DCBiasERA3LB DCBiasERA5LB DCBiasERA2LB DCBiasBBERA3_[1..8] DCBiasQuadMixer DCBiasBBERA2_[1..8] +5VDCin -5VDCin +12VDCin +15VDCin DCBiasERA3HB DCBiasERA2HB DCBiasERA5HB DC Bias DCB_ERA3LB DCB_ERA5LB DCB_ERA2LB DCBiasBBERA3_[1..8] DCB_MIXERS DCBiasBBERA2_[1..8] DCB_ERA3HB DCB_ERA2HB DCB_ERA5HB DCBiasBBERA2_1 DCBiasBBERA2_2 DCBiasBBERA2_3 DCBiasBBERA2_4 DCBiasBBERA2_5 DCBiasBBERA2_6 DCBiasBBERA2_7 DCBiasBBERA2_8 DCBiasBBERA3_1 DCBiasBBERA3_2 DCBiasBBERA3_3 DCBiasBBERA3_4 DCBiasBBERA3_5 DCBiasBBERA3_6 DCBiasBBERA3_7 DCBiasBBERA3_8 MH1 M-HOLE 8-32 MTHOLE_832 MH2 M-HOLE 8-32 MTHOLE_832 MH3 M-HOLE 8-32 MTHOLE_832 MH4 M-HOLE 8-32 MTHOLE_832 MH5 M-HOLE 8-32 MTHOLE_832 MH6 M-HOLE 8-32 MTHOLE_832 U26 PAT-8 1

R11 16.5 SM/C_0805 DCBiasBBERA3_8

2 4

Baseband ERA

Baseband ERA

DCBiasBBERA2_8

2 4

R12 16.5 SM/C_0805

H5-8 DCBias BBin BBout

U27 PAT-9 1 3

H6-8 DCBias BBin BBout

U28 PAT-6 1 3 1 2 3 4 5

2 4

J13 SMA

A

A

2 4

Baseband ERA

Baseband ERA

1 3 5 7 9 11 13

MH7 M-HOLE 8-32 MTHOLE_832

MH8 M-HOLE 8-32 MTHOLE_832

MH9 M-HOLE 8-32 MTHOLE_832

MH10 M-HOLE 8-32 MTHOLE_832

MH11 M-HOLE 8-32 MTHOLE_832

MH12 M-HOLE 8-32 MTHOLE_832 Title Size C Date: FIGURE 2: Top Level: EALFA ANALOG FRONT END Rev X Sheet 1 of 40
1

Document Number Wednesday, April 25, 2007

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1

D

D

U31 MiniCircuits_TCP-2-10 PORT 1 3 R17 100 SM/C_0805 PORT2 C2 4 PORT2 PORT1

SUMPORT

6

SUMPORT GROUND 1

2

C1

C

5

C

C8 1.5p SM/C_0805

C7 1.5p SM/C_0805

B

B

A

A

Title Size A Date:
5 4 3

FIGURE 3:

H1-1: TCP-2-10 Rev X6 Sheet 2
1

Document Number Wednesday, March 07, 2007
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AttCntrl[0..4] AttCntrl0 1DB +5VDCin R23 100 SM/C_1206 R28 22 SM/C_1206 AttCntrl1 2DB R24 100 SM/C_1206 AttCntrl2 4DB R25 100 SM/C_1206 AttCntrl3 8DB R26 100 SM/C_1206 AttCntrl4 16DB R27 100 SM/C_1206

D

D

V5

V4

V3

C

C20 0.01u SM/C_0805 IFin

V2

C19 0.1u SM/C_0805 1 2 3 4

16

15

14

13

VDD RF1 NC1 ACG1 ACG2 ACG3 ACG4

V1 RF2 NC2 ACG6 ACG5 GND

12 11 10 9 17

C21 0.01u SM/C_0805 IFout

C

U35 Hittite_HMC470LP3 HITTITE_HMC470
B

5

6

7

B

C22 0.01u SM/C_0805

C23 0.01u SM/C_0805

C24 0.01u SM/C_0805

C25 0.01u SM/C_0805

8

C26 0.01u SM/C_0805

C27 0.01u SM/C_0805

A

A

Title Size A Date:
5 4 3

FIGURE 4:

H2-1: Programmable Attenuator Rev X6 Sheet 7
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Document Number Friday, April 13, 2007
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D

D

DCBias C9 0.1u SM/C_0805

R18 80.6 SM/C_1206

C

R19 80.6 SM/C_1206 1/4W

C10 0.1u SM/C_0805
C

L1 470n SM/C_0603 U32 MiniCircuits_ERA-3+ MC_VV105 1 3

C11 0.01u SM/C_0805 IFin
B

C12 0.01u SM/C_0805 IFout
B

RFout/DCin 3

A

GND

4 1 RFin

2

GND Title FIGURE 5: H3-1: IF ERA-3 Rev X6 Sheet 9
1

2 4

A

ERA Top View

Size A Date:
4 3

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D

D

DCBias C15 0.1u SM/C_0805

R21 32.4 SM/C_1206

C

R22 32.4 SM/C_1206 1/4W

C16 0.1u SM/C_0805
C

L2 470n SM/C_0603 U34 MiniCircuits_ERA-5+ MC_VV105 1 3

C17 0.01u SM/C_0805 IFin
B

C18 0.01u SM/C_0805 IFout
B

RFout/DCin 3

A

GND

4 1 RFin

2

GND Title FIGURE 6: H3-3: IF ERA-5 Rev X6 Sheet 11
1

2 4

A

ERA Top View

Size A Date:
4 3

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D

D

DCBias C28 0.1u SM/C_0805

R29 107 SM/C_1206

C

R30 107 SM/C_1206 1/4W

C29 0.1u SM/C_0805
C

L3 470n SM/C_0603 U36 MiniCircuits_ERA-2+ MC_VV105 1 3

C30 0.01u SM/C_0805 IFin
B

C31 0.01u SM/C_0805 IFout
B

RFout/DCin 3

A

GND

4 1 RFin

2

GND Title FIGURE 7: H3-5: IF ERA-2 Rev X6 Sheet 13
1

2 4

A

ERA Top View

Size A Date:
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D

DCBias 1 4 5

U40 MiniCircuits_ADE-2 MC_CD542 IF 2 Iout

D

PORT2

3

RF LO

IFin

SUMPORT

R37 26.1 SM/C_1206 1/4W PORT1

R38 36.9 SM/C_1206 1/4W

C44 0.1u SM/C_0805

3

6

4 2

U41 PAT-4 MC_AF320

C45 0.01u SM/C_0805 LOin -3dBm max 1

2

C

H1 TCP-2-10

0 deg

U43 MiniCircuits_ERA-5+ MC_VV105 3

L7 220n SM/C_0603 6 C46 0.01u SM/C_0805

1

C

ISOL

5 R39 49.9 SM/C_0805

IN -90 deg

U42 Synergy_SLQ-K05 SYNERGY_SLQ

GND GND

3 4

2 4

1

1

B

2 4

U44 PAT-4 MC_AF320

B

3

6 LO RF IF 2 U45 MiniCircuits_ADE-2 MC_CD542 1 2 3 Synergy SLQ-K05 Top View 6 5 4 Title Size A Date:
5 4 3

3

Qout

RFout/DCin 3

RFout 3 1 4 5

GND
A

4 1 RFin

2

GND

GND

4 1 RFin

2

GND

A

ERA-5+ Top View

PAT-10 Top View

FIGURE 8:

H4-1: Quadrature Diode-Ring Mixer Rev X6 Sheet 15
1

Document Number Thursday, April 12, 2007
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5

4

3

2

1

D

D

DCBias 1
C

R72 80.6 SM/C_1206 1/4W

C74 10u_16V_C SM/CT_6032_12 2

C

C75 10u_10V_A SM/CT_3216_12 BBin 2 1 1

U58 MiniCircuits_ERA-3+ MC_VV105 3

R73 80.6 SM/C_1206 1/4W C76 10u_10V_A SM/CT_3216_12 1 2 BBout

RFout/DCin 3

GND
A

4 1 RFin

2

GND
A

ERA-2+ Top View

2 4

B

B

Title Size A Date:
4 3

FIGURE 9:

H5-1: Baseband Amplifier ERA-3+ Rev X6 Sheet 17
1

Document Number Friday, March 16, 2007
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40

5


5

4

3

2

1

D

D

DCBias 1
C

R13 107 SM/C_1206 1/4W

C1 10u_16V_C SM/CT_6032_12 2

C

C2 10u SM/CT_3216_12 BBin 2 1 1

U29 MiniCircuits_ERA-2+ MC_VV105 3

R14 107 SM/C_1206 1/4W C3 10u_10V_A SM/CT_3216_12 1 2 BBout

RFout/DCin 3

GND
A

4 1 RFin

2

GND
A

ERA-2+ Top View

2 4

B

B

Title Size A Date:
4 3

FIGURE 10:

H6-1: Baseband Amplifier ERA-2+ Rev X6 Sheet 25
1

Document Number Friday, March 16, 2007
2

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40

5


5

4

3

2

1

D

D

BandLevelMonitor

R41 1.74k SM/C_1206 -20dBm max. for best square law linearity
C

R42 2.4k SM/C_1206

IFin

D1 HSMS-2850 SM/SOT23_123 3 1 C49 100p SM/C_0805

3

INA+

U47A AD8630 SOG.050/14/WG.244/L.325 OUTA. 1

R43 200 SM/C_1206 SQLawOut+

C

R44 54.9 SM/C_1206

2

INAR46 57.6k SM/C_1206 C50 10p SM/C_0805 Square Law Differential Output 100mV / uW R49 200 SM/C_1206 SQLawOutC51 0.01u SM/C_0805 6 R48 10k SM/C_1206

R45 200 SM/C_1206

R47 10k SM/C_1206

B

B

INBOUTB. 7

5

INB+

U47B AD8630 SOG.050/14/WG.244/L.325

Output common mode voltage is 0V 3
A A

Title 1 2 Size A Date:
5 4 3

FIGURE 11:

H7-1: Square Law Detectors with Differential Outputs Rev X6 Sheet 33
1

HSMS-2850 TOP VIEW

Document Number Wednesday, March 21, 2007
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40


5

4

3

2

1

+5VDCin LBAttCntrl[0..4] HBAttCntrl[0..4] LBMon
D

HBMon

C77 0.47u SM/C_0805 XTAL1 8.000MHz ABRACON_ABMM2 3 1

C78 0.47u SM/C_0805

D

7

XTAL1

C79 22p SM/C_0805

C80 22p SM/C_0805 8

VCC VCC

4 6

+5VDCin

+5VDCin C81 0.47u SM/C_0805

4 5

VCC C1+

V+

1 C82 0.47u SM/C_0805

XTAL2 PB0 PB1 PB2 PB3 PB4 PB5 PD2 PD3 PD4 PD5 PD6 PD7

LBAttCntrl[0..4] 12 13 14 15 16 17 32 1 2 9 10 11 LBAttCntrl0 LBAttCntrl1 LBAttCntrl2 LBAttCntrl3 LBAttCntrl4 SCK HBAttCntrl0 HBAttCntrl1 HBAttCntrl2 HBAttCntrl3 HBAttCntrl4 C83 0.47u SM/C_0805

6 2

C1C2+ VC3+

28 27 C84 0.47u SM/C_0805 C85 0.47u SM/C_0805
C

C

+5VDCin

18 20

AVCC AREF ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7

3 HBAttCntrl[0..4] +5VDCin 17 16

C2C3DREN RXEN 26

C86 0.1u SM/C_0805

LBMon HBMon

23 24 25 26 27 28 19 22

R74 0 SM/C_1206 7 9 13 8 10 11 12 14 R75 0 SM/C_1206 R76 NS SM/C_1206 R77 NS SM/C_1206

PD1 PD0
B

31 30 3 5 21

29

RESET

GND GND GND

25 23 19 24 22 21 20 18 15

DR1IN DR2IN DR3IN RX1OUT RX2OUT RX3OUT RX4OUT RX5OUT GND

DR1OUT DR2OUT DR3OUT RX1IN RX2IN RX3IN RX4IN RX5IN

1 3 5 7 9

2 4 6 8 10 J17 CON10A 3M_2510-60XX-XX

B

U59 ATmega48-xxAU TQFP32 J18 CON6A 1 3 5 2 4 6

R116 NS SM/C_0805

+5VDCin J19 CON14A 3M_2514-60XX-XX 2 4 6 8 10 12 14

U60 LTC1348/SO SOJ.050/28/WB.400/L.700

LBAttCntrl4 SCK

LBAttCntrl3 LBAttCntrl0 LBAttCntrl1 LBAttCntrl2 LBAttCntrl3 LBAttCntrl4 1 3 5 7 9 11 13

BLKCON.100/VH/TM2OE/W.200/6
A

HBAttCntrl0 HBAttCntrl1 HBAttCntrl2 HBAttCntrl3 HBAttCntrl4

A

Title Size A Date:

FIGURE 12:

H8: Attenuator Control Interface Rev X6 Sheet 35
1

Document Number Wednesday, April 18, 2007
2

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40

5

4

3


5

4

3

2

1

D

FB1 Ferrite Bead SM/C_1206

DCBiasBBERA2_1

DCBiasBBERA2_[1..8]

D

FB2 Ferrite Bead SM/C_1206

DCBiasBBERA2_2

Power required: +15V@325mA +15VDCin 1 C123 10u_25V_C SM/CT_6032_12

U73 National_LM317MDT TO252/_DPAK 3 IN OUT 2 ADJ

+12V

FB3 Ferrite Bead SM/C_1206

DCBiasBBERA2_3

1

C

R102 2.33k SM/C_0805

R103 274 SM/C_0805

C124 10u_16V_C SM/CT_6032_12

FB4 Ferrite Bead SM/C_1206

1

DCBiasBBERA2_4

C

2

2

2

1

FB5 Ferrite Bead SM/C_1206

DCBiasBBERA2_5

C125 1u_16V_A SM/CT_3216_12

FB6 Ferrite Bead SM/C_1206

DCBiasBBERA2_6

B

FB7 Ferrite Bead SM/C_1206 2 Vout LM317MDT Top View FB8 Ferrite Bead SM/C_1206

B

DCBiasBBERA2_7

DCBiasBBERA2_8

1 Adj.

3 Vin

A

A

Title Size A Date:
5 4 3

FIGURE 13:

H9: DC Bias for Baseband ERA-2 Amplifier Rev X6 Sheet 36
1

Document Number Wednesday, March 21, 2007
2

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40


5

4

3

2

1

D

FB13 Ferrite Bead SM/C_1206

DCBiasBBERA3_1

DCBiasBBERA3_[1..8]

D

FB14 Ferrite Bead SM/C_1206

DCBiasBBERA3_2

Power required: +12V@325mA +12VDCin_BBERA 1 C143 10u_16V_C SM/CT_6032_12

U79 National_LM317MDT TO252/_DPAK 3 IN OUT 2 ADJ

+9V

FB15 Ferrite Bead SM/C_1206

DCBiasBBERA3_3

1

C

R114 1.69k SM/C_0805

R115 274 SM/C_0805

C144 10u_16V_C SM/CT_6032_12

FB16 Ferrite Bead SM/C_1206

1

DCBiasBBERA3_4

C

2

2

2

1

FB17 Ferrite Bead SM/C_1206

DCBiasBBERA3_5

C145 1u_16V_A SM/CT_3216_12

FB18 Ferrite Bead SM/C_1206

DCBiasBBERA3_6

B

FB19 Ferrite Bead SM/C_1206 2 Vout LM317MDT Top View FB20 Ferrite Bead SM/C_1206

B

DCBiasBBERA3_7

DCBiasBBERA3_8

1 Adj.

3 Vin

A

A

Title Size A Date:
5 4 3

FIGURE 14:

H9: DC Bias for Baseband ERA-3 Amplifier Rev X6 Sheet 37
1

Document Number Wednesday, March 21, 2007
2

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40


5

4

3

2

1

+12VDCin_ERA

DCBiasERA2LB

D

D

DCBiasERA2HB

Power required: +12V@220mA

U74 National_LM317MDT TO252/_DPAK 3 IN OUT 2 ADJ

+9V

FB9 Ferrite Bead SM/C_1206 DCBiasERA3LB 1 C127 10u_16V_C SM/CT_6032_12 FB10 Ferrite Bead SM/C_1206 DCBiasERA3HB
C

C126 10u_16V_C SM/CT_6032_12
C

1

R104 1.69k SM/C_0805

R105 274 SM/C_0805

2

1

2

1

C128 1u_16V_A SM/CT_3216_12

Power required: +12V@220mA
B

U75 National_LM317MDT TO252/_DPAK 3 IN OUT 2 ADJ

2

+9V

FB11 Ferrite Bead SM/C_1206 DCBiasERA5LB
B

1

C129 10u_16V_C SM/CT_6032_12

1

R106 1.69k SM/C_0805

R107 274 SM/C_0805

C130 10u_16V_C SM/CT_6032_12

FB12 Ferrite Bead SM/C_1206 DCBiasERA5HB

2

1

2 2 Vout LM317MDT Top View
A

1

C131 1u_16V_A SM/CT_3216_12

2

A

1 Adj.

3 Vin

Title Size A Date:

FIGURE 15:

H9: DC Bias for IF ERA Amplifiers Rev X6 Sheet 38
1

Document Number Wednesday, April 25, 2007
2

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40

5

4

3


5

4

3

2

1

D

+12VDCin

+12VDCin_BBERA +12VDCin_ERA

D

Power required: +12V@135mA

U78 National_LM317MDT TO252/_DPAK 3 IN OUT 2 ADJ 1 C141 10u_16V_C SM/CT_6032_12

DCBiasQuadMixer

C140 10u_16V_C SM/CT_6032_12
C

1

R112 1.69k SM/C_0805

R113 274 SM/C_0805

2

1

2

C

2

1

C142 1u_16V_A SM/CT_3216_12 2 Vout LM317MDT Top View

B

1 Adj.

3 Vin

B

A

A

Title Size A Date:
5 4 3

FIGURE 16:

H9: DC Bias for Quadrature Diode-Ring Mixer Rev X6 Sheet 39
1

Document Number Wednesday, March 21, 2007
2

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40


5

4

3

2

1

D

D

U76 LM317LZ TO92/100 +5VDCin 1 C132 10u_16V_C SM/CT_6032_12 3 VIN VOUT ADJ 2 1 R109 274 SM/C_0805 2 C133 10u_6V_A SM/CT_3216_12 C134 0.1u SM/C_0805 U47E AD8630 SOG.050/14/WG.244/L.325
C

R108 270 SM/C_0805

2

1

C

1 ADJ 2 VOUT

3 VIN LM317LZ Bottom View

2

1

U77 LM337LZ TO92/100 -5VDCin 2 C137 10u_16V_C SM/CT_6032_12
B

11

C135 1u_10V_A SM/CT_3216_12

Power required: +5V @ 10mA -5V @ 10mA

V-

V+

4

3

VIN

VOUT ADJ

2 2 C138 10u_6V_A SM/CT_3216_12

C136 0.1u SM/C_0805

R110 270 SM/C_0805

R111 274 SM/C_0805

1

1

1 ADJ 2 VOUT

3 VIN LM337LZ Bottom View

1

2

C139 1u_10V_A SM/CT_3216_12

A

1

B

A

Title Size A Date:
5 4 3

FIGURE 17:

H9: DC Bias for Square Law Detectors Rev X6 Sheet 40
1

Document Number Wednesday, March 21, 2007
2

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40