Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.naic.edu/~phil/hardware/vertex/jonhagen/ssi.pdf Дата изменения: Mon Feb 4 19:30:26 2008 Дата индексирования: Sun Apr 13 04:35:27 2008 Кодировка: Поисковые слова: закон вина

SSI output provides effective synchronization in a closed-loop control system. A clock pulse train from a controller is used to gate out sensor data: one bit of position data is transmitted to the controller per one clock pulse received by the sensor. Synchronous Serial Interface The Synchronous Serial Interface (SSI), introduced several years ago to simplify absolute encoder interface, has become increasingly popular and is now an unofficial standard recognized by almost all manufacturers of absolute encoders. The physical interface consists of two differential connections aside from power and ground. The controller provides a clock input, and the sensor returns a data signal synchronized to the clock. (see Figure 1.) The sequence of events for the SSI is as follows (see Figure2): Point A The Clock initiates the communications. Normally high, the first falling edge of the clock latches the parallel data. Point B to C The serial data is made available shortly after the rising edge: 540 nanoseconds maximum for the first bid of data; 360 nanoseconds for subsequent data bits. The data is transferred most significant bit first (Gn), least significant last (G0). Point B to D "B to D" indicates the clock signal period. This is determined by the controller, but should less than 15s (~67KHz), and more than 1.08s (~925 KHz). Point F The Final rising edge of the clock, following the last serial bit. The clock should remain high until the next set of data. Point E to G "E to G" is the minimum time before the communication procedure can begin again. It is determined by a monoflop on the sensor side, and is typically 15s to 25s. This is the time required for the monoflop to rearm. With the initial falling edge of the clock, the monoflop causes the parallel data to be latched into a shift register. If the clock signal is to slow (less than 15s), the monoflop will re-arm and restart the process. Model A25 Synchronous Serial Interface Physical Connection and Timing Diagram in .pdf file format.