Äîêóìåíò âçÿò èç êýøà ïîèñêîâîé ìàøèíû. Àäðåñ îðèãèíàëüíîãî äîêóìåíòà : http://www.naic.edu/~kiriaki/MPSP.ps Äàòà èçìåíåíèÿ: Mon Nov 18 00:05:35 1996 Äàòà èíäåêñèðîâàíèÿ: Mon Oct 1 20:29:04 2012 Êîäèðîâêà: IBM-866 Ïîèñêîâûå ñëîâà: ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï ï

AO Pulsar Signal Processor
A Proposal
Abstract
The vastly increased bandwidths provided by the Gregorian Upgrade in the range of
1 í 10 GHz, greatly promote pulsar research at cmíwavelengths, so far a poorly explored
pulsar spectral region. Pulsar signals at these wavelengths, being more immune to dispersive
distortion and irregularities of the ISM, provide a better opportunity to distinguish effects
intrinsic to the source (rotational and emission properties) and allow for mining a deeper
volume of the Galaxy for even more exotic and distant objects. Their steep spectral index,
though, ranging from í1 to í3, sets a sensitivity requirement of wide bandwidth, which
in turn requires more frequency channels to defeat dispersive distortion. On top of this,
sampling at microsecond rates is essential. Here we propose a modular postdetectionísignal
processor based on the NAIC 1024ílag correlator chip. This wideíbandwidth processor,
with a combination of microsecond time resolution, high frequency resolution and kiloílag
correlations, addresses the scientific requirements described above.
1 An Overview of the System
Following the request of the pulsar community expressed at the Pulsar Workshop held at Arecibo
Observatory in October 1995, NAIC plans to construct a modular postdetection correlation signal
processor (AOPSP). This instrument, suitable for the current needs of pulsar research, makes
use of the new capabilities offered by the Gregorian configuration. The processor will satisfy both
folding (synchronous sampling) and search mode requirements, and will facilitate fast dumping as
well as windowing for effective single pulse mode.
It will be built in two phases. A prototype 16íchip Unit will provide up to 50 MHz bandwidth
with full Stokes polarimetry and 9ílevel sampling. Narrower bandwidths in eight octave steps
down to 200 kHz are provided using digital filters. It can also produce 100 MHz BW, full Stokes
with 3ílevel sampling, a pair of 100 MHz BW, dual polarization channels, or 400 MHz in four
independently tunable 100 MHz bands in single polarization. In a second development phase,
three additional 16íchip Units (without the digital filters) will provide total BW up to 800 MHz
in dual polarization. The processor will provide time resolution of 20ïsec with 1024 frequency
lags, and can provide higher time resolution with fewer lags.
2 Instrumental Parameters
Pulsar research entails different experiments that tend to fall into two categories, namely folding
mode where the data stream is synchronously divided into time intervals modulo the topocentric
pulsar period, and search mode where direct output of the data stream is sent to a computer
at very fast IO rates for storage or further processing. 1 . The requirements in the two modes
are different (see Table 1.) The instrumental parameters are set by two pulsar parameters, the
rotational Period (P) (between 1 msec and 5s) and the Dispersion Measure (DM) (between 3 and
currently 800).
1 Note that single pulse studies combine the synchronization requirements of folding with the high output rates
of searching
1

Table 1: Specifications for Folding and Search Mode (one 16íchip Unit)
Parameter Folding Searching
Sample interval ffi t 5 ï s í 300 ms Ö 80 ïs
Number of Lags N lags 32 to 1024 32 to 1024
Number of phase bins N phase 32 to 2048 N/A
Number of polarizations N pol 2 or 4 1y or 2
Available Memory (32íbit) N phase N chan 1,048,576 N/A
Integration time t yy not constrained
Accommodated rates R out ß 3.2 MB/s ß 3.2MB/sec
Number of bits N bits 4,8,16,32 1,2,4
y Two polarizations summed in real time.
yy Limited only by 32bit overflow.
The shortest sample interval ffit is constrained by the speed at which correlation functions of
N lags can be produced and read out (¦ 25 nanoseconds per lag for the NAIC chip). Just as
in frequency space, minimization of aliasing requires at least two sample intervals ffit per time
resolution element.
The data rate out of a correlator for integration time t is calculated for folding as :
R out = N bits
8
N phase N lags N pol
t
Bytes=sec (1)
Forexample timing integrations of 8 seconds give:
(32bits*1024lags*1024phase bins * 4Stokes)/8.0sec = 2 MBytes/s
while for high time resolutions 0.1sec integrations give:
(8bits*256lags*256phase bins * 4Stokes)/0.1sec = 2.5 MBytes/s
The shortest integration time is limited by throughput to tape or disk. This heavy traffic,
calculated for the extreme case of 0.1 sec integration times, accomodates not only folding but
single pulse mode as well. For more reasonable dump times in the folding mode the data rates
scale accordingly. These values are computed for a single 16íchip Unit. For the complete 4íUnit
system the rates are four times as large, so each Unit will be provided with its own CPU and data
storage.
In search mode, the rate is increased by a factor t/ffit, but reduced by the factor 1/N phase :
R out = N bits
8
N lags N pol
ffit
Bytes=sec (2)
For example:
(2bits*512lags*1pol)/80ïs = 1.6 MBytes/s
Hence the output data rate requirements for the two modes are not dissimilar.
2

3 Proposed Implementation
The AOPSP is will have at its second phase four correlator Units (still more can be added if
desired.) A schematic of the full system is shown in Fig. 1.
IF/LO_1 IF/LO_2 IF/LO_3 IF/LO_4 Downstairs
Analog Filtering
2X 50 MHz
or
2X100MHz
IF/LO filtering
Baseband conversion
0íí>500 MHz
Digital filters
0.2KHzíí>25MHz
Correlator
UNIT í 1 UNIT í 2 UNIT í 3 UNIT í 4
50 50 100
100 50 50 50 50 50 50
100 100 100100 100 100
Figure 1: An overview of the AOPSP: Each Unit is an autonomous 50/100 MHz correlator which
contains 4 modules. Each module contains one board with four chips on it, one ALU and
memory of its own. Each Unit has its own CPU and storage.
The current IF/LO system at Arecibo Observatory provides four 500MHz wide subíbands
with two polarizations from each subíband. These overlap in such a way that they provide a total
bandwidth of 1 GHz from 1 to 2 GHz IF. It has been envisaged that soon the second part of the
IF/LO system will provide an additional band 1 GHz wide.
The correlator proposed here will work with the present 1GHz bandwidth (but has the necí
essary spigots for the use with the future 2 GHz IF bandwidth.) Following the prefiltering a
conversion to baseband will be provided. This will allow two central frequencies to be extracted
within each 500 MHz subíband, not necessarily next to each other. The baseband converted signal
then passes through a set of 50 or 100 MHz filters.
Unití1 will have the flexibility of narrower bandwidths by using two sets of digital bandpass
filters, built in house, which provide 8 frequency choices from 25MHz to 195kHz. This feature
would allow two independent narrow band chunks to be placed at opposite ends of the IF range,
for example. Also it would provide for using the AOPSP in finer spectral resolution (at narrower
bandwidths) so that lower than microwave frequencies can be studied polarimetrically, and also
for studies of the ISM.
The correlator Unit follows. Each Unit contains four modules. Each module consists of a
4íchip board that can do EITHER 9ílevel OR bandwidth doubling. The four modules do either
autoí or crossícorrelation, so one 4íboard (16 chip) unit gives:
ffl a) 50 MHz bandwidth, full Stokes, 9 levels -- one frequency chunk
3

ffl b) 50 MHz bandwidth, dual polarization, 9 levels -- two frequency chunks
ffl c) 100 MHz bandwidth, full Stokes, 3 levels -- one frequency chunk
ffl d) 100 MHz bandwidth, dual polarization, 3 levels -- two frequency chunks
ffl e) 100 MHz bandwidth, single polarization, 3 levels -- four frequency chunks
A chunk can be placed anywhere in the 1 GHz bandpass of the IF. In particular, if they are
placed sideíbyíside, the five options give 50, 100, 100, 200 MHz and 400 MHz total bandwidth
respectively, per 16íchip Unit. The desired system would have 4 Units and 8 synthesizers with
200 MHz, 400 MHz and 800 MHz BW, depending on configuration.
Each Unit will provide four outputs, either all four Stokes parameters, dual polarization from
two different frequency chunks, or a single polarization from four frequency chunks. The output
rate is limited to the tapeídrive throughput (3.2 MBytes/s for an Exabyte Mammoth drive) after
the completion of an integration, a time interval specified by the number of lags and phase bins
desired. In search mode two polarizations can be sumed in each Unit, following appropriate
calibration, and 1í 2í or 4íbit clipping will provide packed output data. Data will be transferred
continuously to disk and or tape.
The full version will have four tape drives, one per Unit, while the chosen bus will either
handle the heavy traffic from all four Units or sonsist of four independent output buses. The Unit
computers will most likely be PowerPC VME 64 boards. They will manage the correlation dumps
and operational modes in order to dump the correlator synchronously with the Doppleríshifted
pulsar period. The necessary ephemeris to observe each pulsar will be generated using TEMPO
on a Unix system, (remotely), and transferred to the PowerPC. This will allow remote access to
the machine.
4 Simplified IF/LO Description
A description of the IF/LO system (Fig. 2) is needed to understand the proposed system. The
Upstairs system selects a band of up to 1 GHz wide from each polarization in the RF bandpass
of the receiver and feed. This selection is made using the 1 st LO, a computer controlled HP
Synthesizer covering 10 MHz to 20 GHz, normally operated at a frequency above the RF band
of the receiver (''highíside'' LO). The resulting signals lie in the 1í2 GHz 1 st IF band. Gain and
delay adjustment under computer control can be carried out. This signal power is brought down
to the control room on optical fibers. The optical signal is demodulated back to 1í2 GHz, and
the signal levels gainíadjusted under computer control. The two signals then go through 4íway
splitters.
The downstairs system has eight identical units, four for each polarization. Each of the four
polarization pairs has its own 2 nd LO, another HP computer controlled synthesizer, and a choice
among three antiíaliasing filters ahead of the 2 nd mixer covering 1000í1500 MHz, 1500í2000 MHz
or 1250í1750 MHz. The four pairs are completely independent and they can have the same or
different filters. The output of the 2 nd mixers is in the 0í500 MHz range. Each of the eight units
is split into eight identical outputs, one of which is dedicated to the AOPSP.
4

D
C
B
A
IF/LO Schematic (Simplified)
1st LO
1st IF
(identical for second polarization)
(one polarization shown)
1í2 GHz Fiber
0í500 MHz
...
...
...
...
F1
F2
F3
F4
(1 km)
Passband (1í1.5,1.25í1.75
or 1.5 to 2 GHz)
2nd LO
4 ' s
(1.5 to 2 GHz)
Figure 2: A simplified schematic of the upstairs/downstairs IFLO system. Only one polarization
branch is shown.
AOPSP Analog and A/D
F1
F2
F3
F4
300 íí 400 MHz
Filter
400 MHz
0í50
0í100 MHz
Lowípass
Filter
A/D
A/D
A/D
A/D
200 Msamples/sec
8bit digitizer demultiplexing
RHC
RHC
LHC
LHC
A
B
or
Bandpass
C
D
Figure 3: The analog input and the digitization part.
5

Filters
50,100 MHz
RR
RL
LR
LL
16íChip UNIT # 1
(configured for full Stokes )
L
R
A/D
A/D
Digital
Digital
Filters
25,12.5..0.2MHz
8íbit digitizer
Filter
Analog
BUS
EXA
BYTE
Power
PC
Figure 4: The digital part of Unit 1, producing 4 Stokes with 50MHz bandwidth 9ílevel or 100
MHz bandwidth, 3ílevel. Each module produces one Stokes parameter in folding mode.
5 AOPSP Analog Processing and A/D Conversion
The first 16íchip Unit has four inputs (Fig. 3), two from LHC distribution units A and B, and
two from RHC distribution units C and D. This allows up to four different frequency chunks of
50 or 100 MHz bandwidth to be selected. In this case all four 2 nd LO synthesizers will be set
differently. If two dualípolarization chunks are desired, first LO synthesizer pairs are set to the
same frequency. If all four Stokes parameters are desired, all four 2 nd LOs are set to the same
frequency.
The input signals pass through a computer controlled attenuator followed by a bandpass filter
computeríselected as either 50 or 100 MHz bandwidth. A fixedífrequency downconverter brings
the signal to base band where it is sampled in an 8íbit A/D converter clocked at 200 MHz. This
data stream is deímultiplexed and fed into either the digital filters or directly to the correlator
chip modules.
The second, third and fourth Units are identical to the first except that they have no digital
filters. Ideally, Units 3 and 4 will be fed from a toíbeíconstructed copy of the IF/LO system,
which will provide a completely separate first LO and use another pair of optical fibers. This will
provide simultaneous access to the full 2 GHz bandpass of the short wavelength receivers. An
interim solution may provide just four additional 2 nd LO synthesizers, as a fixedítuned offset from
the existing 2 nd LOs.
6 The Digital Part
Following baseband conversion and filtering, four 8íbit analog to digital converters are needed per
Unit (see Fig. 3). This digitization is more than adequate to account for the 40dB dynamic range
often seen in single pulse work. The signal at the digitizer is dispersed anyway, so the dynamic
range provided is more than sufficient. The digital filters use all 8íbits while the correlator uses
either 9 level or 3 level values derived from the 8íbit samples.
6

Filters
Filters
A/D
A/D
A/D
A/D Filters
Filters
8íbit digitizer
25,12.5..0.2MHz
100 & 50 MHz
RR_1
LL_1
RR_2
LL_2
Digital
Digital
Digital
Digital
16íCHIP UNIT # 1
(configured for Dual polarization)
L_1
R_1
L_2
R_2
EXA
BYTE
BUS
PPC
Figure 5: The digital part of Unit 1 in 9ílevel 50 MHz or 3ílevel 100 MHz mode, producing total
power of two pairs of 50 or 100 MHz placed at different parts of the IF as desired. In single
polarization the frequency span can be doubled by placing each of the four inputs in a different
part of the RF bandpass.
The two basic configurations which provide either 9ílevel sampling or 3ílevel sampling are
presented in Fig. 4 and 5.
The correlator chip will be operated conservatively at 100 MHz clock rates. It produces up
to 1024 either auto or cross correlation lagged products. It contains 1024 32íbit accumulators,
and an output buffer in the form of a 32íbitíwide by 1024ílong shift register. At the end of the
sample time ffit the accumulator contents are transferred to the output buffer on the chip and
the accumulators are cleared to zero. This takes less than a microsecond. Its fast dump rate
of 25nanosec/lag means that full 1024ílag dumps can be made every 25microsec while the chip
simultaneously accumulates the next integration. When fewer lags are adequate one can obtain
sample intervals scaled proportional to the number of lags.
In the 9ílevel mode each one of the 4íchips on one board will produce either the High order
ternary product, HH, Lowíorder product, LL, or a cross product HL or LH as shown in Fig. 6.
In the 3ílevel bandwidthídoubling mode, the Oddí and Evení numbered outputs replace the
Highíand Lowíorder Ternary Samples, giving OO, EE, OE and EO accumulations on the four
chips.
The correlator board has a programmable interface (Arithmetic Logic Unit) that is capable
of handling the fast dumps necessary to search for and study fast pulsars. The Arithmetic Logic
Unit consists of a fast adder and a memory of 3 X 1MWord*32bit. The Unit's memory can be
thought of as four arrays of 1024 lag products by 1024 pulse phase bins, though the ratio of lags
to phase bins is up to the observer. Each correlation is added to the appropriate pulse phase bin.
The memory is divided into three buffers which are flipíflopped for read and write operations.
The triple buffering scheme proposed by Bill Sisk is as follows. One buffer will be used normally,
as the data output buffer, while the other two are used for active data taking. These two will
alternate each sample interval ffit as the READ memory and the WRITE memory, so that he does
not have to do his readímodifyíwrite cycle into the same memory. In this way he can run the
7

3ílevel 9ílevel
OO
OE
EO
EE
HH
HL
LH
LL
modify
read
write
save
correlator
chips
ALU Memory
blocks
Data
BUS
100 MHz clock 20/40 MHz
clock
1MWordX32 bit each
(e.g. 1024lagsX1024bins)
Figure 6: One correlator module contains 4 chips, one ALU and triple buffered memory containing
1024x1024x32bit storage each.
read, the modify, and the write operations all in parallel, in principle gaining a factor of two in
speed (in practice, letting him use memory which runs a factor of two slower).
In the folding mode the ALU+memory configuration can run as fast as 40MHz, allowing for
fast output rates to be accomodated. This will allow a time resolution of 25 microseconds with
1024 lags. This is twice the nominal 20 MHz output clock rate, but has been tested successfully
on the chips.
7 Data Transmission and Storage
this part is not finalized yet
The BUS
The Power PC
The tape Units
Phase 1 ...
Phase 2 ...
8 Generation of synchronous dumps
9 Time Plan/People/Pricing
The current plan is to have Unit 1 functioning by the end of 1997. This would require budgeting
the purchasing of components within the next fiscal year. Given the shortage of man power Bill
Sisk could start working on the board design by late fall. Perhaps a technician could start filling
the boards by Christmas 1996. The data transmission would require some experience with Power
PCs, the current concept for data handling, which will probably mean Phil starting on this late
spring 97.
8

Quantity Quantity ITEM PRICE
Unit 1 4 Units ANALOG + A/D
IF preprocessing
4 16 gain control
4 16 Analog Filters 50 MHz
4 16 Analog Filters 100 MHz
4 16 8íbit digitizers
4 4 digital filters
DIGITAL
4 16 Correlator cards each having 4 chips and
12 Mbytes of memory
(triple buffer memory scheme)
1 1 (or 2 or 4 ?) Card crates with power supply
1 4 host cpu board for card control (Power PC)
1 1 (?) time generation and card control
1 4 interface cards for data output
WORKSTATION
1 1 workstation for data taking
1 4 (or more) data storage device (tapeídrives)
1 4 data storage
9