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Physica C 326 ­ 327 Z1999. 83 ­ 92

Single flux quantum comparators for HTS AD converters
A.Yu. Kidiyarova-Shevchenko a,b, D.E. Kirichenko c , Z. Ivanov a, ) , F. Komissinsky d , E.A. Stepancov e, M.M. Khapaev f , T. Claeson a
Chalmers Unióersity of Technology, Gothenburg, Sweden Nuclear Physics Institute, Moscow State Unióersity, Moscow, Russia c Physics Department, Moscow State Unióersity, Moscow, Russia d Institute of Radio Engineering and Electronic RAS, Moscow, Russia e Institute of Crystallography RAS, Moscow, Russia Computer Science Department, Moscow State Unióersity, Moscow, Russia
b a

f

Received 25 April 1999; received in revised form 28 July 1999; accepted 2 September 1999

Abstract We have investigated different comparators for Flash and S ­ D high temperature superconducting ADCs designed using three-layer HTS tri-crystal junction integrated circuit technology with spread of the junction critical currents less than 10% and features size 0.6 m m. Using the theoretical estimations for the bit error rate in RSFQ circuit under the restrictions of the given technology, we have estimated working temperature as T s 62 K. At this temperature, the circuits were optimized in order to achieve maximum performance of the related ADCs in terms of input bandwidth, resolution and operating margins. For design purposes, a novel method was developed for inductance calculation with 3D magnetic field distribution in multilayer superconducting technology and extraction of the inductance matrix of the equivalent circuit. q 1999 Elsevier Science B.V. All rights reserved.
Keywords: Comparators; RSFQ; HTS superconductors; AD converters

1. Introduction There is a vast number of conceivable circuit designs for ArD converters. The most popular of them are: integration types, counter types and parallel types. Each approach has characteristics that make it most useful for a specific class of applications, based on speed, accuracy and hardware cost. From the general structure of the ArD converters we can extract two components that mostly define the key properties of conversion -- analog signal
)

Corresponding author.

conditioner and comparator. Analog signal conditioners Z``analog-to-analog'' converters. are used to make the input signal suitable for conversion. Analog comparators make an elementary choice between the magnitude of two inputs and decide which is greater. This is the equivalent of a one-bit ArD conversion. The ArD conversion process usually calls for a number of decisions; they may be made sequentially by a single comparator or simultaneously by a whole string of comparators, as in `` flash'' converters. The accuracy Zin fraction of LSB., a number of effective binary bits N, linearity, and speed Zinput

0921-4534r99r$ - see front matter q 1999 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 1 - 4 5 3 4 Z 9 9 . 0 0 4 8 4 - 0


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bandwidth f . are primarily affected by the properties of the comparator and signal conditioner. The dependence between N and f for the sine-wave reference signal is given by the following equation, where T is the conversion time: 1 T 2y
N

fs

.

Z 1.

In superconductive circuitry, the analog signal conditioners are naturally realized using the effect of magnetic flux quantization. This effect means that in a superconductive loop broken by Josephson junctions there is a circulating current which is a function of the applied magnetic flux. There are many different signal conditioning circuits employing magnetic flux quantization depending of the ADC type and type of the digital code. It can be, for example, Quasi One Junction SQUID ZQOJS. w1x or double junction interferometer w2x or S ­ D modulator w3x. In any case, the circulating current has to be sampled to determine its direction. One direction is arbitrarily assigned as digital `` 0'' and the other as digital ``1''. In the most modern designs, a serial connected pair of overdamped Josephson junctions Zbalanced comparator. w4x electrically coupled with the input loop is used for digitizing purposes. The output digital signal is in the form of single flux quantum ZSFQ. pulses w5x that can be further processed with RSFQ superconductive digital devices w6x. In the last 10 years, the great progress was achieved in understanding and designing superconductor ArD converters. The best-reported performances of superconducting low temperature ADCs currently are 14 bit, 20 MSrs for counter type w7x and 6 bit, 10 GSrs for flash type w8x. The speed of SFQ circuits is determined by the Ic R n product of the employed Josephson junctions. For currently standard 2 m m niobium process the characteristic time constant is typically f 6 ps and decreases linearly with minimum linewidth. During the last 5 years, significant effort was made to establish niobium technology with submicron Josephson junctions. Up to now only single cells with few junctions were experimentally tested and the best achievement is a T Flip-Flop operating up to

750 GHz with 2 mArm m2 critical current density of the Josephson junctions w9x. Another very prospective approach is to use high-temperature superconductor ZHTS. Josephson junctions. These junctions exist in various types but in general they have very high Ic R n up to 8 mV w10x at the helium temperature and natural non-hysteretic I ­ V curves. This means that characteristic time constant T can be rather small close to f 200 fs. But to realize ArD converter in high-Tc technology is not an easy feat due to a number of theoretical and technological restrictions that are related to the nature of the high-Tc Josephson junctions. Up to now there have been done only a number of demonstrations of HTS digital circuits in a level of the 10 ­ 20 junctions w11,12x. Most of them were created in bicrystal technology providing reasonable spread of the critical currents. In this work, we investigate different comparators for flash and S ­ D high temperature superconducting ADCs designed using three layers HTS tri-crystal junction integrated circuit technology. This work was done through the following steps: optimization of the circuits without noise and technology restrictions on inductances, theoretical calculation of the bit error rate ZBER. and comparators current sensitivity in a presence of thermal noise, reoptimization with the inductances extracted from the layout. In conclusion, general restrictions on the HTS technology for RSFQ circuits are discussed.

2. Comparators optimization A typical circuit of SFQ-driven converter with balanced comparator is composed of three parts Zsee Fig. 1.: clock pulse input driver, balanced comparator and output pulse conditioner. SFQ clock-driven pulses with frequency fsa m p are passed through the JTL to the interferometer ä J 7, J 6, J 3, J 24 that includes the balanced comparator formed by junctions J 3, J 2. Each pulse induces a 2p-leap of the Josephson phase in either junction J2 or junction J 3, depending on whether the measured current Isi gn is larger or smaller than a threshold It . The switching of the J 2 junction means that a SFQ pulse is


A.Yu. Kidiyaroóa-Sheóchenko et al. r Physica C 326 ­ 327 (1999) 83 ­ 92

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Fig. 1. Equivalent circuit of the typical SFQ-driven converter with balanced comparator.

switching. At this frequency, the threshold uncertainty or digitizing error in terms of AD conversion can be found varying the current increasing rate. As is shown in Fig. 2, the final threshold uncertainty is less than 5% of Icmi n . All circuit parameters ZFig. 2Zb.., except critical currents of the decision making pair, have margins larger than 30%. The margins for critical currents of the Josephson junctions in the balanced comparator are not higher than 3%. This means that a small distortion of the balance between these two junctions strongly influences the threshold and its uncertainty. In order to investigate the performance of the QOJS comparator, we have used the same circuit connecting the balanced comparator with QOJS loop ä J 1, L14 Zsee Fig. 3.. Therefore, the signal current to

developed across it. This pulse then passes the output conditioner that amplifies its energy. There is also a region in parameter space where both junctions of the comparator can switch simultaneously. This effect leads to some uncertainty of the threshold D It and also to the appearance of extra flux inside the input interferometer that will affect the sample pulse propagation. Typically the effect of double switching can be avoided during optimization, but it still occurs Zas it will be shown later. in the HTS case where the parameters are limited by hard technology restrictions. In order to avoid propagation of the SFQ pulse back to input JTL in case of double switching of junctions ä J 2, J 34 junction J 6 is added into the circuit. The circuit has been simulated and optimized to find working parameters correspondent to peak performance conditions: maximum operational frequency, minimum threshold uncertainty and the largest parameter margins. All simulations were done with the help of the PSCAN program w13x in values normalized on the critical current of the smallest Josephson junction Icmi n and Ic R n product. The values of inductances and resistors are normalized corre s p ondingly o n the b l s F 0 r 2 p Icmin and Ic R nrIcmi n . The optimization was done under the condition that the measured signal is a linear function of the time within the range "Icmi n . It was found that maximum operational frequency is about fsa m p s 0.06 vc and limited rather by the switching time of the input interferometer then the errors in comparators

Fig. 2. Digitizing error of balanced comparator at clock frequency f s 0.06 vc Za. and table of optimum working parameters Zb..


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Fig. 3. Equivalent circuit of the QOJS comparator with SFQ sampling.

be sampled by the balanced comparator is the current through junction J 1 in the QOJS interferometer. For the linear reference input signal the current I J 1 is a periodic function of analog input current with the period F 0rL1 and mean value equal to zero. The parallel combination of the N QOJS comparators can be naturally applied for construction of the flash type ADC with N effective bits gray coding of the digital data w14x. There is a dynamic hysteresis in the current phase characteristic of QOJS. It was shown in Ref. w15x that the width of hysteresis became smaller for larger ration Ic2 r Ic1 and sm aller param eter b l s F 0r2p Ic1 L1. This width should be kept smaller than half of the period of the loop current in order to have the accuracy of the ADC less than 1r2 LSB. Under this condition we have found the dependence between frequency of the input current and b L for linear reference signal with amplitude F 0rL 2 and ratio Ic2 rIc1 s 3 Zsee Fig. 4Za... As a result, for LSB comparator the maximum input frequency that corresponds to b L s 0.4 is close to f 0.014 vc ZFig. 4Zb... With the obtained maximum input frequency and QOJS parameters Z Ic2 rIc1 s 3, b L s 0.4. the remaining part of the circuit operates with the parameters calculated for the balanced comparator itself. For obtained maximum input signal frequency for LSB comparator, the relation between resolution of ADC and input bandwidth is given by Eq. Z1.. For typical value of Ic R n f 2 mV for HTS Josephson junctions, the maximum LSB frequency is f 176 GHz that will give maximum bandwidth of flash

type ADC not higher than f s 2 GHz with resolution of N s 6 bits. The same procedure was followed for investigation of a S ­ D modulator Zsee Fig. 5Za... Following the approach of Przybysz w3x, a S ­ D modulator was constructed as a combination of superconductive inductor L1 and resistor R1. The current to be sampled by the balanced comparator is the current through the inductor IL1. In the ideal case with high accurate sampling for constant input signal Isi gn the current IL1 is a periodic function of time with period T s F 0rIsign R1 and amplitude F 0rL1 ZFig. 5Zb... We have simulated S ­ D with R1 s 0.005, L1 s 2 and input frequency equal to f s 2.1 = 10y3 vc . The circuit has demonstrated correct operation with the parameters obtained for the balanced comparator.

Fig. 4. Definition of the hysteresis width of I J 1Z t . dependence in QOJS Za. and maximum input frequency fsi g n for 1-bit flash ADC with the accuracy less than 1r2LSB as a function of QOJS b L Zb..


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thin films with 200 nm thickness were deposited using a laser ablation technique at oxygen pressure Z0.3 mbar. and temperature Z7308C.. An in-situ Au film of 20 nm thickness was deposited using the laser ablation method to provide protection from air of the YBCO film, followed by a thick 200 nm Au film obtained by the e-beam evaporation system. Patterning of the microbridges through the grain boundary lines ZJosephson junctions. and the circuits geometry was made using e-beam lithography and ion-beam milling with feature size 0.6 m m. Resistive lines and contact pads were fabricated from Au and insulated from the YBCO pattern by an amorphous CeO 2 insulating layer, obtained by laser ablation technique.

Fig. 5. Equivalent circuit of the S ­ D modulator with SFQ sampling Za. and time dependence of the current in the quantizing loop for constant input signal Zb..

The resulting oversampling ratio for the maximum input frequency and maximum sampling frequency is f r fsa m p s 24.

3. Technology process The fabrication sequence used consists of Z1. substrate alignment markers etching for determination of the grain boundaries positions, Z2. YBCO film and in-situ gold film deposition, Z3. gold deposition for e-beam lithography markers, Z4. YBCO e-beam patterning, Z5. dielectric deposition and ebeam patterning, and Z6. gold deposition and e-beam patterning for bias resistors and contact pads. The substrate material is a YSZ. Each substrate contains three symmetric bicrystal lines with missorientation angle a s 248. The alignment markers were patterned in the substrate using ordinary photolitography and ion-beam milling techniques. The positions of these markers to the grain boundary lines were obtained with an accuracy of about 1 m m. YBCO

Fig. 6. Comparison of the Jc ZT . dependencies of the 248 bicrystals junctions between three test chips Za. and between three grain boundaries on the one chip Zb..


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Under equal conditions, three chips were fabricated with the test structures containing 24 Josephson junctions per chip Zeight junctions per each grain boundary. with linear size w s 2­8 m m. We have tested 36 junctions from all the chips and found that with yield of 13% perfect RSJ like behavior can be observed under the conditions w - 4l J . The resulting spread of the Jc and R n between different grain boundaries and between different chips is not higher than 10%. The average critical current density at helium temperature is equal to Jc Z4.2 K. s 2.5 = 10 5 Arcm2 and is a linear function of temperature Zsee Fig. 6.. The average value of the Ic R n product is equal to 3 mV Z4.2 K..

4. Thermal noise analysis It is important that all key parameters of the circuit such as working temperature, minimum critical current Icmi n , Ic R n and minimum inductance of the loop are defined only by the BER. For most general purpose applications, the level of the BER can be taken as 10y16 1rbit. This means that circuits with integration of about 10 3 bits with operational frequency of about 20 GHz will work without any fault during at least 8 min. A theoretical analysis was developed w16x that is based on the consideration that in general the influence of noise in RSFQ circuits can be estimated from the probability P of error switching in a pair of junctions in a balanced comparator: P s 1 y erf

Therefore, the relationship expressed in Eq. Z2. and Eq. Z3. gives the value of the BER as a function of k s IcrT Zin units wm ArKx.. Under the restriction of the given technology there are three fixed parameters that will define the k parameter: critical current density Jc Z4.2 K. s 2.5 = 10 5 Arcm2 , film thickness d s 0.2 m m and liner size of the Josephson junctions w ) 2 m m. From the l J ZT . dependence, restriction that w - 4l J and critical currents need to be varied between 1 and 2 Icmi n follows that minimum working temperature should be higher than T s 62 K. At this temperature, the critical current of the smallest Josephson junction is equal to Ic s 300 m A that corresponds to the k s 4.83 wm ArKx and through Eq. Z2. Zwith margins 30%. to BER f 10y14 . As a result, the estimated working temperature is T s 62 K and corresponding units of current and voltage in the simulation are respectively 300 m A and 420 mV, resulting in units of resistance, inductance, frequency and time which are respectively 1.4 V , 1.09 pH, 1.27 THz, 0.78 ps.

5. Comparators design Several circuits were suggested for low-frequency and high-frequency ``dc'' experimental investigations of comparators based on bicrystal Josephson junctions: balanced comparator, QOJS comparator with SFQ sampling, QOJS comparator with dc sampling, S ­ D comparator. Following the same line as was done for the simulations of the different comparators, all circuits have the similar element, balanced comparator. For low frequency experiment, there are also included

z

'p

It y I D It

/

,

Z 2.

where D It is the effective threshold uncertainty and Z It y I .rIc can be considered as a margin for critical current. The effective threshold uncertainty D It depends of many parameters and in particular of clock driver output impedance ZZ v .. For HTS circuits based on bicrystal junctions because of large inductances one can apply results of theory in the thermal fluctuation and low speed operation Z < ZZ v . < 4 R n . limits. D It w m A x s 23 = 10
3

z

2p k B T

2r 3

F

0

/

Ic1

r3

w m Ax . Z 3.

Fig. 7. Equivalent circuit for QOJS comparator low frequency testing.


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Fig. 8. Layout of the QOJS comparator with SFQ sampling based on HTS bicrystal Josephson junctions.

dcrSFQ and SFQrdc converters. Following the approach in Ref. w11x we have realized the SFQrdc converter as a double junction SQUID-driven by the SFQ pulses. This approach requires an additional external control signal for reset operation of the SQUID. The number of junctions was reduced to the smallest possible value in order to maximize circuit yield. The typical equivalent scheme of the experimental circuits ZQOJS with SFQ sampling . for lowfrequency testing is presented in Fig. 7. Under the design rules developed for given technology, the layout of the circuits was created. In Fig. 8, the corresponding layout is shown. In these circuits, Josephson junctions are formed as the microbridges with the minimum length 3 m m over the bicrystal lines. Therefore, a double junction interferometer is formed as a plane loop around the submicron slit in the superconductive film. In these structures, magnetic field is essentially 3D in nature. The kinetic inductance can be compared with magnetic energy inductance because the
Table 1 Extracted from layout parameters of QOJS with SFQ sampling L 4 s 2.02 L9 s 0.875 LW 4 s 1.57 J2s2 JW 3 s 1 L6 s 3.46 L10 s 1.183 LW 3 s 2.24 J3s1 JW 1 s 1.8 L1 s 3.9 LS1 s 2.85 LW 2 s 2.24 J 4 s 1.2 JW 2 s 1

values of the London penetration depth are compared with the thickness of the layers and rapidly increase with working temperature. These facts significantly hamper accurate inductance calculations for such devices and practically exclude the application of existing software. In order to overcome the difficulties, a new program 3D-MLSI Z3D MultiLayer Superconducting Inductances. for inductance extraction was developed Zsee Appendix A.. With the help of this software package, the inductances in the equivalent circuits were extracted Zsee Table 1.. Due to the absence of a ground plane and a number of topology restrictions, the calculated minimum loop b l was about f 5. The simulation with the extracted large inductances demonstrated that a large value of the b l parameter leads to the possibility to store one or more flux quanta inside the balanced comparator loop. This affects the performance of the comparators. As a result, the maximum sampling frequency was decreased to fsa m p s 0.01 vc with the same accuracy of digitizing and operational margins of only 15%.

6. Conclusion We have investigated the properties of the QOJS comparator and S ­ D modulator for the RSFQ ArD converters. Optimization without influence of noise and restrictions on the inductances, the circuits demonstrated correct operation up to sampling frequency fsa m p s 0.06 v c with 30% margins of the circuit parameters. The digitizing error for both circuits is about 5% of minimum critical current. The maximum input frequency of the LSB of flash type ArD converter was determined as a function of b L of the QOJS comparator loop that corresponds to the fsi gn s 0.014 vc Z b L s 0.4.. A HTS integrated circuit technology with Josephson junctions that are formed across three parallel

L 2 s 4.77 LS 2 s 2.91 LW 1 s 2.56 J 5 s 1.2 I 1 s 0.8

L5 s 2.41 LW 0 s 3.8 LW 10 s 3.12 J 6 s 1.0 I 3 s 1.09

L7 s 0.0 LW 5 s 0.875 J1s1 JW 0 s 1 IS1 s 1.69


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248 grain boundaries placed 20 m m apart on ZY.ZrO 2 substrates was developed. The quality of the Josephson junctions was tested on three chips with 32 junctions on each and a spread of less than 10% in junction critical current was determined. The analysis of the circuit noise immunity based on the given technology parameters Z Jc Z4.2 K. s 2.2 = 10 5 Arcm2 , Ic R n Z4.2 K. s 3 mV. showed that operational temperature for the designed circuit can be up to 62 K with BER 10y14 . Under the established design rules, several circuits were designed for low-frequency experimental investigation of the comparators. The inductances of the equivalent circuits were extracted with the help of a newly developed method of inductance calculation in 3D-distribution of magnetic field. Due to the absence of a ground plane and a number of topology restrictions, the calculated minimum loop b l was about f 5. The simulation with the extracted large inductances demonstrated changing of the circuits dynamics that affected the performance of the comparators. As a result, the maximum sampling frequency was decreased to fsa m p s 0.01 vc with the same accuracy of digitizing and operational margins of only 15%. As a result, we can once more confirm the already known statement that HTS bicrystal technology is not suitable for fabrication of highly integrated RSFQ devices operated at high frequency. However, this technology allows one to investigate some basic properties of rather simple circuits and to check the correctness of design tools and approaches that are developed. There are a few alternative HTS technologies w3,10x suitable for fabrication of RSFQ circuits with small inductances and higher operational frequency. High frequency operation, however, demands much higher critical currents to compensate the thermal noise. In case of high speed operation with small value of input impedance ZZ v . < R n the threshold uncertainty in the balanced comparator is given by the following equation w16x: D It w m A x s 10 2p
3

junctions critical currents. For example with BER s 10y16 Z k s 32. and temperature T s 40 K, the critical current should be Ic s 1.2 mA. One can calculate the maximum critical current that can be reached in a given technology assuming that linear dimensions of the junctions are equal to 4l J . This critical current is independent of critical current density and given by following equation: Icmax s 16 l2 Jc s 16 J

F

0 0

2p d I m

,

Z 5.

where d I is a magnetic space between two electrodes and in most cases can be taken as 2 l L . From Eqs. Z2. and Z5. follows the relation between maximum working temperature and k Zor correspondent BER.. This dependence for typical HTS parameters ZTc s 86 K, l L s 0.2 m m. is presented in Fig. 9 under the condition that in the circuit Josephson junctions have a normalized critical current between 1 Icmi n and 3 Icmi n . Therefore, we have found that the desired value of BER defines the operational temperature that in turn defines the minimum critical current being used during optimizations. Area of the largest junction is defined by 4l J and is a function of critical current density Jc . If it is possible or not to reach the obtained working temperature depends on the technology capabilities in junction sizes and Jc . For example, for BER s 10y16 and corresponding k s 32 m ArK the maximum working temperature is T s 27 K, and the minimum value of the critical current is

z

2p k B T

1r 2

F

0

/

Ic1

r2

w m Ax .

Z 4.
Fig. 9. Working temperature for RSFQ HTS circuits as a function of k s Ic r T defined by BER.

In that case, the coefficient k s IcrT m ArK is considerably larger and leads to a high value of the


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Icmi n s 864 m A. For standard photolitography feature size of 2 m m the latter corresponds to Jc s 20 = 10 3 Arcm2 .

Acknowledgements Authors thank M.Yu. Kupriyanov and T.F. Filippov for support and helpful discussions. The work was mainly supported by the ESPRIT grant HTS-RSFQ and in part by the projects INTAS97-1712 and ISTC N11-99.

Appendix A. Equivalent circuit inductances extraction The program package 3D-MLSI is based on a new mathematical model. This mathematical model is derived from the London equations and takes into account planarity of the structure, finite thickness of layers of metallization and dielectric, and 3D structure of magnetic field. The superconductivity current density is presented by use of a potential representation called stream function or T-function. The stream function is a single scalar unknown function in the problem. The full and correct setting of the boundary value problem for integro-differential equations for stream function is obtained. The terminal currents and currents circulating around holes in superconductors are introduced by simple boundary conditions of the first kind in a way similar to boundary conditions for the Laplace equation. The matrix of self- and mutual-inductances is introduced by use of the functional of full energy. The same inductance matrix allows one to calculate fluxoids. For the numerical solution of the problem, the finite element method on a triangular mesh with linear finite elements is used. For these finite elements, the current density is simulated by circulating currents with piecewise-constant density. The program package contains a powerful triangular mesh generator. More information about mathematical model, numerical technique and examples of calculations can be found in Refs. w17,18x. An important part of the program package is the preprocessor part. The structure of input data is very rich and flexible and allows us to calculate large and

complicated devices. In order to solve the problem to import the shape of conductors and other parameters from layout data presented in certain CAD form, we have developed a converter from DXC format w19x data to internal 3D-MLSI format. The converter can parse the physical layers sequence and extract conductor thickness and shape. Another problem in device simulation is the definition of a set of linear independent currents for inductances matrix extraction. We solve this problem in close connection with equivalent circuit representation of the physical device w20x. We consider socalled fundamental loops in the circuit. Any other loop within the circuit can be presented as the unification of fundamental loops. Each loop uniquely defines the current path and the sequence of terminals in the layout. Also, each loop defines the sequence of oriented inductances in the equivalent circuit. The program 3D-MLSI calculates a physical inductance matrix for the currents in fundamental loops. Then it is possible to set equal schematic and physical fluxoids in fundamental loops and to calculate the values of inductances in the equivalent circuit. We realized the schematic inductance calculation algorithm in the limits of the analytical calculations program MAPLE. The details of this technique will be published elsewhere. References
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w10x

w11x

w12x

w13x