Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.cplire.ru/html/lab234/pubs/2011_14.pdf Дата изменения: Sat Sep 17 17:30:54 2011 Дата индексирования: Tue Oct 2 08:49:25 2012 Кодировка: Поисковые слова: m 5

High-Harmonic Phase Detector based on SIS junction
Konstantin V. Kalashnikov*, Andrey V. Khudchenko*, Valery P. Koshelets* and Andrey M. Baryshev




*

Institute of Radio Engineering and Electronics, IREE, Moscow, Russia

SRON Netherlands Institute for Space Research, Groningen, the Netherlands

Abstract
A novel superconducting element, High-Harmonic Phase Detector (HPD), intended for phase-locking of a Flux Flow Oscillator (FFO) in a superconducting integrated receiver (SIR) has been proposed and experimentally tested. According to our concept a high harmonic of a reference local oscillator (LO) signal (frequency of about 20 GHz) produced in the SIS junction is mixed by the same junction with FFO signal (frequency of order 600 GHz); the HPD output is applied directly to the FFO control line to correct its phase and frequency. To realize efficient FFO phaselocking the HPD output signal is maximized by tuning the HPD bias voltage, the RF power, the LO power and frequency (harmonic number). Calculated 3D dependences of the HPD output signal power versus bias voltage and LO power correspond well to experimental measurements. To demonstrate that the FFO signal has been phase-locked by the HPD we used an additional SIS-mixer with receiving antenna and monitored its intermediate frequency (IF) output. The regulation bandwidth (BW) of the phase-locking loop (PLL) system based on the HPD as wide as 70 MHz has been measured experimentally; that value several times exceeds the BW of regular PLL systems used for cryogenic oscillators. New PLL system based on HPD synchronizes up to 92% of the emitted FFO power (this parameter is called the spectral ratio, SR) for free running FFO line as wide as 12 MHz The HPD PLL system is simple and compact, therefore it is very promising for future SIR applications, especially for building multi-pixel SIR arrays and for phase-locking of the THz range FFO.

Theoretical and experimental study of Harmonic Mixer based on SIS junction
When two signals of frequencies f1 and f2 are applied to the SIS junction, the signals on every combination frequency f = nf1 ±mf2,n,m N appear. Let us consider the smallest frequency signal, i.e. IIF = ak cos(2 (f1+kf2)t+0k). Thus, the harmonic mixer operates as a high-harmonic phase detector and could be used for phase locking loop system. It is crucial to achieve a high-power output signal of the harmonic mixer based on the SIS to realize efficient FFO phaselocking. The theoretical study of the HM power characteristics has been performed. The results of numerical calculations coincide well with experimental measurements. When two signals of frequencies 635 GHz and 18 GHz (its 35-th harmonic is used) are applied to the HM based on the Nb-AlOx-Nb SIS junction (size 1x1 um2 with Rn of about 25 Ohm), the maximal output power is about -90 dBm.

Experiment

Calculated power characteristics of Harmonic Mixer based on SIS junction Theory

New approach for FFO Phase-Locking
Block Diagram of the Superconducting Integrated Receiver
4 K dewar SIR chip
SIS mixer
Harmonic mixer FFO as LO
350-700 GHz

FFO Spectrum locked by HPD
-5 -10 -15
Power (dBm)
Free run, LineW idth = 16.8 MHz Lock by RT PLL, SpectralRatio = 6 % Lock by HPD PLL, SpectralRatio = 84%

Concept of FFO synchronization by Harmonic Phase Detector
Local Oscillator

ALMA LO
(band 9)

HEMT 4-8 GHz

Referenc e 20 GHz

IF Processor & Digital Auto Correlator Computer controlled data acquisition system

-20 -25 -30 -35 -40 -45 -50 3,90 3,95 4,00 Frequency (GHz) 4,05 4,10

~ 20 GHz LFT

~ 600 GHz

HPD
FFO
~ 400 MHz ~ 604 GHz SIS mixer ~ 4 GHz

~ 0 MHz

HEMT Electronics FFO, SIS, HM control

PLL

4 G Hz

LSU

Spectrum Analyzer

400 MHz reference

In the SIR the FFO is phase-locked by a conventional room temperature (RT) PLL system. The traditional PLL is a semiconductor-based device designed for 300 K, and it cannot be placed directly in the cryostat. Due to the total delay of about of 17 ns in connection cables, the BW for RT PLL is limited by 12 MHz .

We proposed to use harmonic mixer for phase-locking of the FFO to an external reference by applying the HPD output directly to the FFO control line. It allows us to place all the PLL elements close to the FFO. So the delay in the loop decreases, and as result the bandwidth can be increased up to 100 MHz .

The HPD PLL has been experimentally implemented. The results of the FFO spectra measurements prove the HPD PLL concept and demonstrate its efficiency. The regulation bandwidth of HPD PLL system of about 70 MHz has been measured. For the FFO line as wide as 17 MHz the HPD PLL phase locked up to 85% of emitted by FFO power, which is incomparably more than 6% synchronized by the traditional RT PLL for the same FFO line.

Comparison HPD PLL with analogues
Phase Noise of FFO locked by HPD
10 0
H PD

Summary
The novel application of the SIS junction ­ the Cryogenic High-Harmonic Phase Detector (HPD) has been proposed. The theoretical and experimental studies of the HM are performed; measured results are in a good qualitative and quantitative agreement with numerical calculations. The concept of the HPD is experimentally realized; regulation bandwidth of the HPD PLL as wide as 70 MHz has been demonstrated. High efficient FFO phase locking (SR > 90% for the FFO linewidth of 12 MHz) and considerable decrease of the FFO phase noise have been achieved.

-70

Spectral Ratio (%)

Phase Noise (dBc)

80

-80

60
E x p e r i m e n ta l D a ta RT P L L , = 14 M H z 1 C r yo P L L , = 2 5 M H z 1 C r ioP LL , > 4 0 M H z H P D P LL, = 7 0 M H z S i m u l a t i o n (b y A . P a n k r a t o v , e t c . ) R e g u l a ti o n d = 1 0 M H z R e g u l a ti o n d = 2 0 M H z R e g u l a ti o n d = 3 0 M H z R e g u l a ti o n d = 1 0 0 M H z

-90
R o o m T e m p e ra tu r e P L L Lo c k b y H P D
5

40

20

-100 10

10

6

10 O f fs e t (H z )

7

10

8

0 0, 1

1

10

100

Characteristics of some PLL systems
Delay, ns BandWidth, MHz LW for SR > 90 %, MHz SR for LW = 22 MHz, % RT PLL CryoPLL1 17 9 14 25 1,6 3,2 2 15 HPD PLL <4 70 12 77

L in e W id th (M H z )

Comparison with other FFO synchronization systems (RT PLL, CryoPLL 1) shows that proposed approach has definite advantage over the conventional PLLs. High efficiency, small size, low power consumption and simplicity make the HPD attractive for future applications, such as ultra wide baseline interferometry and development of receiver array.
1

Detailed information about CryoPLL could be found in the article A.V. Khudchenko et.al. "Cryogenic Phase Locking Loop System for Superconducting Integrated Receiver ", SuST , 22, 085012, 2009.

For further information please contact: kalashnikov@hitech.cplire.ru

Institute of Radio Engineering and Electronics, Moscow, Russia