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Cryogenic Phase Locking Loop System for Flux Flow Oscillator
Andrey Khudchenko1, Valery Koshelets1, Pavel Dmitriev1, Andrey Ermakov1, Oleksandr Pylypenko2
2State 1Institute of Radio Engineering and Electronics, IREE, Russia Research Center of Superconducting Electronics "Iceberg", Ukraine

Abstract
A bandwidth of the typical Phase Locking Loop (PLL) system for the Superconducting Integrated Receiver (SIR) is limited by unavoidable delays in the long cables between SIR inside cryostat semiconductor PLL system outside it. To overcome this limitation we propose Cryogenic Phase Locking Loop (CPLL).The CPLL has been developed for phase locking of a Flux-Flow Oscillator (FFO) in the SIR. The main element of the CPLL is a cryogenic phase detector (CPD) based on a superconductor ­ insulator ­ superconductor (SIS) tunnel junction. All the loop elements are placed at 4.2 K inside a cryostat with the FFO; so the novel CPLL system has a loop length only 50 cm. The CPLL operating frequency has been increased from 400 MHz up to 4 GHz to decrease a loop filter delay to 0.5 ns. As a result the total loop group delay is about 4.5 ns. Such a small delay results in a CPLL synchronization bandwidth as wide as 40 MHz and allows to phase-lock more than 60% of the emitted by FFO power even for FFO linewidth about 11 MHz. This fraction of phase-locked power is three times large than can be achieved with conventional room-temperature PLL. We have realized an integrating loop filter for the CPLL. Such a filter sufficiently increase stability and decrease a phase noise of the FFO phase-locked by the CPLL.

Frequencies and substances selected for the first TELIS flight
## FFO Frequency, GHz 1 2 3 4 5 6 7 8 495.04 496.88 505.6 507.28 515.25 519.25 607.78 619.1 H2-18O HDO BrO ( = 0.3 !!) ClO O2 /pointing /pressure BrO ( = 0.3 !!) O3 isotopes HCl (HOCl, ClO) Substances (High priority)

TELIS-MIPAS at Esrange, Sweden; March 2009

TELIS: successful flight of 12 hours on 30 kilometers altitude! The SIR developed by SRON and IREE for TELIS has been able to measure the ozone depleting component brome oxide in the stratosphere from a gondola of high­altitude balloon. The SIR channel provided valuable scientific data during the whole flight; these data are under elaboration right now.

Example of measured atmospheric spectra.

Ultrawideband PLL is required (>50 MHz):
For the future SIR applications (f>1THz) an FFO with the NbN electrodes will be used; the FFO linewidth could considerably exceed 10 MHz. The specification for a ALMA interferometer require a phase stability better then 75 fs. To realize such a stability for the SIR a part of phase locked FFO power ­ Spectral Ratio (SR), as high as 90% is needed.

Superconducting Integrated Receiver
4 K dewar SIR chip
SIS mixer Harmonic mixer FFO as LO 550-650 GHz 20 GHz reference

HEMT 4-8 GHz

IF Processor & DAC

Computer controlled data acquisition system Electronics FFO, SIS, HM control

HEMT
4 GHz

PLL

LSU

400 MHz reference

Dependence of the SR vs FFO linewidth for different of the vs linewid fo di er PLL bandwidths. The PLL bandwidth is determined by a total group delay in the loop. A bandwidth of the typical PLL system for the SIR is limited by unavoidable delays in the long cables between the SIR inside a cryostat and semiconductor PLL system outside it. To overcome this limitation we propose the CPLL.

Schematics of the FFO stabilization circuit. FFO frequency is mixed in HM with the 19-21 GHz reference. The mixing product is amplified, downconverted and compared with the is mplifie downconverted with 400 MHz reference in the PLL. The phase difference signal generated by PLL is used to feedback the FFO control line.

CPLL Loop Elements:
1 - FFO with HM in shield 2 - HEMT amplifiers 3 - CPD and Loop filter in the box Loop length is 0.5m.

Concept of the Cryogenic PLL
Spectrum Analyzer 600 GHz 20 GHz 4 GHz

SIS - Cryogenic Phase Detector for the CPLL
300 250
90

FFO
Harmonic Mixer Loop Filter

1
HEMT

SIS Current (A)

200 150 100 50 0 -50

Autonomus signal 1 in phase contra phase Phase response 3 2 4

85

1

I sis, A

80 75 70 65 0 60 120 180 240 300 360

CPD 2
Cryostat T = 4.2 K LO 4 GHz

Phase Differnce

5
0 1 2 3 4 5

SIS Voltage (mV)

I-VCs of a SIS junction. Microwave signals (5 GHz) are applied. (5 GHz ar

CPD based on SIS demonstrates sinusoidal response in dependence on phase difference between two incoming microwave signals.

All the elements of the Cryogenic PL Loop are inside the cryostat with a FFO. It allows to minimize the loop length and the time delay.

Photo of the CPLL in cryostat. FFO and CPD are placed in two separated shields.

Results for FFO phase-locking with CPLL
A u to n o m u s (L W = 2 M H z ) C r yo P L L (o p e r a tio n a l f = 4 G H z ) R o o m T e m p er at u r e P L L 0 -5 -1 0
P, dBc

Summary
A new and successful application of a SIS junction success of SIS junction cryogenic phase detector (CPD). (CPD).
The CPD intrinsically could operate with an effective CPD intrinsically wit an bandwidth more than 100 MHz. The maximal output more MH maximal signal is about 0.1 mV. 0.1 mV Concept of the CryoPLL system has been proven. Cr oPLL en. Bandwidth as wide as 40 MHz has been obtained. obtained. Th improvement The improvement of the phase locked FFO spectral ocked ratio from 20% to more than 60% has been achieved at from 20% to 60% application of the CryoPLL for FFO linewidth 11 MHz. of CryoPLL for 11 MH CryoPLL has an integrating filter for active phasefilter activ elocking, stabilization and low phase level noise. level noise.
For further information please contact: Khudchenko@hitech.cplire.ru June 2009.

RoomPLL CryoPLL
Loop length()

-55 -60 -65 -70

Room Temperature PLL CryoPLL (no intergating filter) CryoPLL with intergating filter

2 5 15
3 40 360 3 80 40 0 f , M Hz 4 20 440 4 60 480

0.5 2 4.5 40!
dBc

-1 5 -2 0 -2 5 -3 0 -3 5 -4 0
320

Delay in elements (ns)

-75 -80 -85

Total Delay (ns)

-90 -95 100 1000 10000 100000 1000000 1E7 1E8

Bandwidth (MHz)

Offset from carier , Hz

12
Downconverted spectra of FFO. Demonstration of the CPLL advantage: bandwidth = 40 MHz it gives SR = 95% for 2 MHz linewidth compare to SR=82% for the Room Temperature PLL system.

Phase noise of the FFO phase-locked with: "1" ­RT PLL; "2" ­ CPLL without integrating loop filter; "3" - CPLL with integrating loop filter. The CPLL demonstrate a Phase Noise lower then for the Room Temperature PLL at frequencies more then 1kHz .