Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.atnf.csiro.au/people/Suzy.Jackson/thesis.pdf Дата изменения: Wed Apr 8 08:36:12 2009 Дата индексирования: Tue Oct 2 03:18:29 2012 Кодировка: Поисковые слова: annular solar eclipse

University of Technology, Sydney Faculty of Engineering

Interface Electronics for the Australia Telescope Compact Array
by

Suzanne Amanda Jackson
Student Number: 97051597 Ma jor: Telecommunications Engineering Supervisor: A/Prof Sam Reisenfeld Industry Co-Supervisor: Graham Moorey (CSIRO ATNF)

A 12 Credit Point Project submitted in partial fulfilment of the requirement for the degree of Bachelor of Engineering February 2003



Synopsis
I have been employed by the CSIRO Australia Telescope National Facility (ATNF) for much of the duration of my studies towards the Bachelor of Engineering. Early in my career with the ATNF, it became evident that the AT dataset hardware which we had made great use of over the years would have to be re-thought, especially given the increasing complexity of upcoming receivers for the Ma jor National Research Facilities (MNRF) upgrade. The germ for this pro ject was planted late one night at Parkes observatory, whilst faultfinding an interface unit for the Parkes conversion system, a module which provides extra functionality for an AT dataset. Much of the interface hardware was realised in programmable logic, and it occurred to us that it would be possible, and indeed useful, to re-engineer the core of the dataset functionality using programmable logic, so that it was no longer tied to a specific processor, or indeed set of hardware. This thesis seeks to document much of the progress to date towards the goal of a simple, re-useable dataset engine, as well as the implementation, using this engine, of an interfacing system for the MNRF millimetre receivers on the Australia Telescope Compact Array. It covers some background information on the AT dataset protocol, the development of a VHDL model describing the protocol, and several instances of hardware making use of the protocol. Of particular interest are the efforts at reducing RFI emanations from the receiver interface, as well as the design of an ultra low noise ADC subsystem for the water vapour radiometer. Finally, the thesis documents some of the test software used along the way to prove system operation, as well as some of the systems integration and pro ject management hurdles experienced throughout the course of the pro ject.

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Statement of Originality
This thesis is the result of work undertaken between 2000 and 2003 in the Department of Telecommunications Engineering at the University of Technology, Sydney, and the CSIRO Australia Telescope National Facility. Work on the Australia Telescope dataset protocol is based upon work carried out at the Australia Telescope National Facility between 1985 and 1990, principally by Richard Ferris. Further developments on this work were carried out in consultation with Mr Ferris, and George Graves, of the Australia Telescope Receiver Group. Mechanical fabrication of components for this thesis was carried out by technical staff of the Australia Telescope, both at the Marsfield Radiophysics Laboratory, and the Narrabri Compact Array Observatory. Similarly, assembly of production versions of printed circuit boards for this thesis was carried out by technicians at the Radiophysics Laboratory. Overall top level design of the interfacing system, including the decision to use optical fibre to connect the millimetre receivers back to the antenna control computers, was done in conjunction with Graham Moorey, head, Australia Telescope Receiver Group. Dataset protocol 'C' libraries used within the Australia Telescope were incorporated in the test software written for this pro ject. The author of these libraries is unknown. A L TEX 2 code written by Dr Shaun Amy of the Australia Telescope National Facility was utilised as a template for this thesis. This thesis contains no material which has been presented for another degree at this or any other university and, to the best of my knowledge and belief, contains no copy or paraphrase of work published by another person, except where duly acknowledged in the text.

Suzanne A. Jackson February 2003

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Acknowledgements
I feel a debt of gratitude towards a large number of people, both for assistance over the course of this pro ject, and also over the course of my studies. First and foremost must come my supervisors, Graham Moorey and A/Prof Sam Reisenfeld, for their unfailing support over the last eight months. My colleagues within the Receiver Group also bear special mention, both as a rich source of ideas and inspiration, and also for helping in every step of the way in taking these ideas and creating practical hardware from them. In particular, I must thank Henry Kanoniuk, George Graves, Mark Bowen, Eliane Hakvoort, Les Reilly, Alex Dunning, and Jennifer Lie. Numerous people in the ATNF workshops at Marsfield and Narrabri Observatory have also been of great assistance, machining metal and installing equipment where required, and on occasion showing great patience when not everything worked as expected. Dr Dave McConnell, Dave Brodrick, Dr Mike Kesteven, and Simone Magri have been extremely helpful in debugging software aspects of this pro ject, and have written large amounts of code to make these interface units work with AT online computing systems. Graeme Carr^ analysed huge amounts of data from the water vapour radiometer ad acquisition system, whilst Dr Peter Hall, and Dr Robert Sault offered help in setting design goals for the system. Dr Shaun Amy provided invaluable assistance in the typesetting and layout of this document, as well as kind and considerate advice, and lending an ear where warranted. Finally I must thank my partner, Perry Armstrong, who has stood by me throughout the trials, tribulations, and occasional successes that have made up this degree. Without his unfailing emotional support, none of this would have been possible.

A The presentation of this thesis was made possible through the use of L TEX 2.

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Abstract
The Australia Telescope National Facility runs a synthesis array near Narrabri comprising six 22m dishes. New receivers are being built for these antennas to cover 16-26GHz and 85-115GHz. As part of this upgrade, interface modules for the receivers must be designed and built, and these interfaces must be connected back to the antenna control computers. These interface units will allow numerous analogue and digital variables to be interrogated via a high speed fibre optic interface. Close proximity to the receiving feedhorns dictate that particular attention must be paid to radio frequency emissions. The interfaces will make use of programmable gate arrays, for which firmware will be developed using schematic and VHDL. This thesis covers the design and implementation of the interfacing hardware and software for these new receivers.

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Contents
List of Tables List of Figures 1 Intro duction 1.1 Overview . . . . . . 1.2 Australia Telescope 1.3 Receiver Interfacing 1.4 Precis of Work . . xiii xv 1 1 1 3 4 5 5 5 5 6 6 6 7 7 8 9 10 12 13 14 14 15 16 18 19 20

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2 Literature Review 2.1 Introduction . . . . . . . . . . . 2.2 VHDL Literature . . . . . . . . 2.3 Compact Array Documentation 2.4 Xilinx Design Documentation . 2.5 RFI Mitigation . . . . . . . . . 2.6 Labwindows/CVI Coding . . . .

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3 Dataset Engine 3.1 Introduction . . . . . . . . . . . . . . 3.2 AT Dataset Protocol . . . . . . . . . 3.2.1 Request Format . . . . . . . . 3.2.2 Response Format . . . . . . . 3.2.3 Packet Padding and Response 3.2.4 Function Address Partitioning 3.2.5 Parallel Buss . . . . . . . . . 3.3 VHDL Coding . . . . . . . . . . . . . 3.3.1 UART Design . . . . . . . . . 3.3.2 Protocol Engine Design . . . . 3.3.3 Simulation and Testing . . . . 3.4 Schematic Instantiation . . . . . . . . 3.5 Summary . . . . . . . . . . . . . . . ix

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x 4 Receiver Interfaces 4.1 General Interfacing Requirements 4.2 F83 Interface . . . . . . . . . . . 4.2.1 RFI Mitigation . . . . . . 4.2.2 PCB Design . . . . . . . . 4.2.3 FPGA Design . . . . . . . 4.3 Conversion Interface . . . . . . . 4.3.1 PCB Design . . . . . . . . 4.4 Local Oscillator Interface . . . . . 4.4.1 PCB Design and Packaging 4.5 Water Vapour Radiometer . . . . 4.5.1 PCB Design . . . . . . . . 4.5.2 FPGA Design . . . . . . . 4.6 Testing . . . . . . . . . . . . . . . 4.7 Summary . . . . . . . . . . . . . 5 Test 5.1 5.2 5.3 5.4 5.5 Software Overall Requirements . . . Dataset Libraries . . . . . Dataset Test Code . . . . Receiver Monitor Panel . . Water Vapour Radiometer 5.5.1 Server . . . . . . . 5.5.2 Client . . . . . . . Summary . . . . . . . . . ... ... ... ... Code ... ... ... ject ... ... ... ... .. ... . . . . . . . .

Contents 21 21 22 22 24 26 27 27 28 29 29 30 32 33 37 39 39 40 40 41 42 42 43 45 47 47 47 48 49 49 49 51 51 51 53 55 55 60 71

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6 Systems Integration and Pro 6.1 Overview . . . . . . . . . . 6.2 Fibre Cabling . . . . . . . 6.2.1 Fibre Mux . . . . . 6.2.2 Fibre Modems . . . 6.3 Pro ject Management Issues 6.4 Summary . . . . . . . . .

Management ......... ......... ......... ......... ......... .........

7 Conclusions and Future Work 7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bibliography A AT A.1 A.2 A.3 Dataset Engine VHDL Source UART Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dataset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F83 ADC Sequencer Source . . . . . . . . . . . . . . . . . . . . . . . .


Contents A.4 F83 Bus Controller Source . . . . . . . . . . . . . . . . . . . . . . . . . A.5 WVR ADC Sequencer Source . . . . . . . . . . . . . . . . . . . . . . . B F83 Interface Schematics C WVR Interface Schematics D Conversion Interface Schematics E LO Interface Schematics F Fibre Mux Schematics G Labwindows/CVI Source Co de G.1 Dataset Test Panel . . . . . . . . G.1.1 dataset serv.c . . . . . . . G.2 Receiver Monitor Panel . . . . . . G.2.1 mm rx.c . . . . . . . . . . G.3 Water Vapour Radiometer Server G.3.1 wvr.c . . . . . . . . . . . . G.4 Water Vapour Radiometer Client G.4.1 wvr client.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xi 74 77 83 97 105 111 115 117 117 117 127 127 133 133 146 146


xii

Contents


List of Tables
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 4.1 4.2 4.3 Dataset request packet composition . . . . . . . . . . . . . . . . . . Dataset request special characters . . . . . . . . . . . . . . . . . . . Dataset monitor reply packet composition (no errors or warnings) . Dataset command reply packet composition (no errors or warnings) Dataset error register bit allocations . . . . . . . . . . . . . . . . . Dataset response special characters . . . . . . . . . . . . . . . . . . Control function address partitioning (D3) . . . . . . . . . . . . . . Monitor function address partitioning (D3) . . . . . . . . . . . . . . Dataset serial format . . . . . . . . . . . . . . . . . . . . . . . . . . Common baud rate dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 11 11 12 13 13 15 16 26 26 26

HFE4074 fibre transmitter specifications summary . . . . . . . . . . . . HFD3023 fibre receiver specifications summary . . . . . . . . . . . . . . Compact Array receiver interface fibre link budget . . . . . . . . . . . .

xiii


xiv

List of Tables


List of Figures
1.1 1.2 3.1 3.2 3.3 3.4 3.5 3.6 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 5.1 5.2 5.3 5.4 6.1 B.1 B.2 B.3 B.4 B.5 B.6 B.7 ATNF Compact Array antennas, in compact configuration with solid panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compact Array millimetre receiver prototypes . . . . . . . . . . . . . . AT dataset buss structure . . . . . . . . . A "D2" dataset module . . . . . . . . . . . VHDL dataset parallel buss monitor timing VHDL dataset parallel buss control timing VHDL dataset simulation run . . . . . . . Dataset schematic symbol . . . . . . . . . F83 interface card . . . . . . . . F83 ADC schematic . . . . . . . Conversion interface card . . . . Local oscillator interface card . WVR interface card . . . . . . . WVR data acquisition schematic WVR ADC reference histogram F83 interface test board . . . . F83 interface RFI test setup . . F83 interface RFI results . . . . Dataset test panel screendump . Receiver monitor panel . . . . . Water vapour radiometer server Water vapour radiometer client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ... .. ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 7 8 14 15 19 19 22 24 28 29 30 31 32 34 35 36 40 41 43 44 48 83 84 85 86 87 88 89

... ... panel panel

Fibre mux board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F83 F83 F83 F83 F83 F83 F83 interface interface interface interface interface interface interface pro ject sheet . . . . . . . ADC schematic . . . . . digital I/O 1 schematic . digital I/O 2 schematic . RFI filtering schematic . Xilinx support schematic power supply schematic . xv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


xvi B.8 B.9 B.10 B.11 B.12 B.13 B.14 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 D.1 D.2 D.3 D.4 D.5 D.6 F83 F83 F83 F83 F83 F83 F83 interface interface interface interface interface interface interface Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx pro ject sheet . . . . . . . . . . comms schematic . . . . . . . . address decode schematic . . . address buss schematic . . . . local ports schematic . . . . . . ADC sequencing schematic . . transceiver direction schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110

WVR WVR WVR WVR WVR WVR WVR WVR MM MM MM MM MM MM

interface interface interface interface interface interface interface interface

pro ject sheet . . . . . . . ADC schematic . . . . . RFI filtering schematic . digital I/O schematic . . DAC schematic . . . . . Xilinx support schematic power supply schematic . Xilinx schematic . . . . . interface interface interface interface interface interface

conversion conversion conversion conversion conversion conversion

pro ject sheet . . . . . ADC schematic . . . . connector schematic . digital I/O schematic . Xilinx schematic . . . power supply schematic

E.1 MM local oscillator interface schematic . . . . . . . . . . . . . . . . . . 112 E.2 MM local oscillator interface Xilinx schematic . . . . . . . . . . . . . . 113 F.1 MM fibre mux schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 116


Chapter 1 Introduction
The engineer's first problem in any design situation is to discover what the problem really is. Unknown

1.1

Overview

The Australia Telescope National Facility (ATNF) is a division of the Commonwealth Scientific and Industrial Research Organisation (CSIRO) charged generally with the administration and development of radio astronomy in Australia, and more specifically with the operation of telescopes for use by Australian and international researchers. The ATNF operates three installations; the 64m Parkes radio telescope, the 22m Mopra radio telescope, and an array of six 22m radio telescopes at Narrabri, termed the Australia Telescope Compact Array (ATCA). As a result of the Working Nation report the ATNF was awarded an $11m grant in 1995 in order to upgrade the Narrabri Compact Array telescope to operate at millimetre wavelengths (DIST 1995). In addition to upgrades to the antenna surfaces and provision of extra stations to support short baseline interferometry, a substantial component of this upgrade is the design and manufacture of six new millimetre wave receivers, covering frequency bands of 16-26GHz and 85-115GHz (Moorey et al. 2002). In order to facilitate control and monitoring of these receivers from the antenna control computers, a new programmable logic based "dataset" was developed. This design serves as the core enabling technology for an interfacing subsystem to allow computer control of the receivers and associated electronics via optical fibre. This thesis covers the design and development of the dataset based interfacing hardware used to control these receivers, as well as software written to test the hardware and issues encountered in the implementation of the system.

1.2

Australia Telescope Receiver Group

The Australia Telescope (AT) receiver group has its origins in the birth of the science of radio astronomy, immediately following World War 2. In the past fifty years, the AT 1


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CHAPTER 1: Introduction

Figure 1.1: An aerial photo showing five ATNF Compact Array antennas, in a compact millimetre-wave configuration, with new solid panels in place. The North/South spur can be seen extending from the main line towards the left of the photograph.

Figure 1.2: Two Compact Array millimetre receiver prototypes, undergoing cool down tests in the Narrabri receiver workshop. Much of the ancillary equipment, such as the down conversion modules and Water Vapour Radiometer, are missing in this picture.


CHAPTER 1: Introduction

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receiver group (originally the radiophysics receiver group) has designed and constructed numerous receivers for telescope installations in Australia and overseas. Some of the more noteworthy examples of late are the Galileo receiver; an ultra low noise, narrow band deep space communications receiver designed specifically to support the NASA Galileo mission, following the near disastrous mishap which prevented the spacecrafts' main high gain dish from unfurling. Utilising a synthesis array composed of the 64m dish at Parkes, and the 70m dish at Tidbinbilla, NASA scientists were able to download some 70% of the expected Galileo mission data. The Parkes telescope has also been given a new lease of life, thanks to the commissioning of a 13 beam 21cm Hydrogen "multibeam" receiver, comprising a massive dewar supporting 26 independent low noise amplifiers and associated electronics. The receiver group consists of some sixteen engineers and technicians, covering the fields of cryogenics, RF and MMIC design and assembly, and digital electronics design.

1.3

Receiver Interfacing History and Background

The development of the Australia Telescope Compact Array, in the 1980s, posed numerous control and monitoring challenges for AT engineers, principally in terms of how to control a large, highly distributed electromechanical system with the utmost in reliability, at low cost, whilst producing a minimum of unwanted Radio Frequency Interference (RFI) that might be picked up by the sensitive receivers. Prior to the development of the Compact Array, AT receiver systems had no remote monitoring. Telescopes typically used only a few simple receivers, consisting of a basic RF signal chain and cryogenics. Should something go wrong, the only way to tell was that the signal disappeared. Configuration changes, such as changing frequency, were done manually. The "AT dataset" with its accompanying protocol, was developed in the late 1980s to fulfil this need. The protocol is a simple asynchronous serial command/response string, whereby registers within different equipment may be interrogated or changed by providing an address and data string. Previous AT receivers connected to a dataset via a single ended parallel buss. The dataset then connected back to the Antenna Control Computer (ACC) via a serial line. In order to mitigate the effects of RFI from the datasets, they were physically located separately from the receiver feedhorns. As part of the MNRF receiver development, a new interfacing scheme is also being developed for use with the new receivers. This interfacing scheme must maintain a high level of software compatibility with previous incarnations, whilst improving on the original dataset design by being smaller, cheaper, faster, and most importantly quieter (in terms of electromagnetic interference).


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CHAPTER 1: Introduction

1.4

Precis of Work

This capstone pro ject details a subset of the development work for the MNRF receiver interfacing. This is a continuing pro ject, starting in approximately 1999, and is expected to continue in some form well past the deadline for thesis submission. As such, this thesis can only hope to capture a portion of this development and implementation effort. Chapter 2 details the process of literature review that was undertaken as part of this pro ject. Chapter 3 goes into the development of the "dataset engine", a simple VHDL model describing the operation of the AT dataset protocol, so that the protocol may be implemented in programmable logic. Chapter 4 covers the design of most of the physical modules that make up the receiver interfacing subsystem, and details some of the design challenges that were overcome in order to realise the pro ject. Of particular interest are the RFI challenges posed by these units, as well as the ADC subsystem of the water vapour radiometer interface. Chapter 5 discusses some aspects of the various test programs that were used in the commissioning of the prototype receivers. Chapter 6 details aspects of the systems integration effort, required to patch all these systems together and update the Compact Array antennas to use fibre optic communications. This chapter also covers the pro ject management issues encountered over the course of the pro ject. In Chapter 7, the pro ject as a whole is reflected upon, detailing what has been achieved, and what is still to be done. The appendices contain documentation which is of interest as reference material, such as system schematics and code.


Chapter 2 Literature Review
Study the past if you would define the future. Confucius

2.1

Introduction

As this thesis is part of an ongoing pro ject, the process is not easily broken up into literature review, design, implementation etc. Instead, each subsystem of the pro ject has been treated in this manner, so the literature review, like other aspects of the development process, is a necessary adjunct to other work, and is revisited where necessary. In order to make some sense of the chaos, this literature review has been broken down into subsections, which whilst they do not reflect a chronological progression, certainly do represent a logical ordering of ideas for the pro ject.

2.2

VHDL Literature

The seed for this pro ject was germinated whilst studying Advanced Digital Systems, in which the Very high speed logic Hardware Description Language (VHDL) was a ma jor topic. VHDL is a key enabling technology for this pro ject. The text for this sub ject (Yalamanchili 1998) was initially useful, but proved to be focused more on simulatable rather than synthesisable VHDL code. My primary reference whilst designing the VHDL subsections used in this design was Synopsis (1998). This reference proved an invaluable resource. In addition, I came across a useful compendium of VHDL code in Smith (1996), which provided numerous examples which were of use in this pro ject.

2.3

Compact Array Do cumentation

The Australia Telescope Compact Array is a large, complex instrument. Much useful information about the online computer systems and monitoring systems is available in The Australia Telescope Compact Array Users' Guide (1999). A succinct coverage of 5


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CHAPTER 2: Literature Review

the monitoring schema was found in Hall et al. (1992). Descriptions of the AT Dataset protocol were obtained from Ferris (1991). With such a large instrument, much remains unwritten. A lot of useful information and ideas for dataset use were thus gleaned from discussions with Dick Ferris, who designed the original datasets, and Simone Magri, who has written Unix device drivers for them. Details of the previous receiver interface were found in Sinclair et al. (1992) and Reilly (1997). Further information was provided by Les Reilly, Henry Kanoniuk, Graham Moorey, and George Graves, in the form of design documentation (schematics etc) and advice.

2.4

Xilinx Design Do cumentation

Xilinx publishes a series of application notes on their website dealing with a myriad of design issues with Xilinx devices, including configuration schemes and design tips for the different families of FPGA. The Xilinx libraries guide (Xilinx 1993) was an invaluable published resource, as was the Xilinx databook (Xilinx 2002). Rather than use Xilinx configuration PROMs, I chose to use Atmel In System Programmable (ISP) parts. The Atmel (Atmel 2002) application note was of great use here. In addition were the notes on the Atmel in system programmer (Atmel 2002) which I built rather than buy.

2.5

RFI Mitigation

Good references on RFI mitigation and design practices, with practical advice and a minimum of "sacred cows" proved hard to find. One useful book was White and Mardiguian (1985), which contains a lot of good practical advice on coupling, grounding, and shielding, with plenty of graphs providing good "rule of thumb" values for different situations. This was an area where the experience of the senior engineers within the receiver group proved invaluable.

2.6

Labwindows/CVI Co ding

No work involving the C language is complete without a reference to the seminal work on the sub ject, the "white bible" (Kernighan and Ritchie 1988). Whilst deceptively thin, this volume serves as a definitive reference for C syntax and semantics. Stevens (1994) provides a similarly useful introduction to TCP/IP, whilst Wright and Stevens (1995) gives lots of details of code and algorithms for connecting computers via TCP. The Labwindows Libraries Guide (National Instruments 1996) and Labwindows getting started guide (National Instruments 1996) were also useful compiler references.


Chapter 3 Dataset Engine
The major difference between a thing that might go wrong and a thing that cannot possibly go wrong is that when a thing that cannot possibly go wrong goes wrong it usually turns out to be impossible to get at or repair. Douglas Adams

3.1

Introduction

In order to control and monitor low bandwidth systems on the Compact Array, equipment, such as receivers, conversion modules, power supplies etc. are connected to an "AT Dataset" (Hall et al. 1992). The dataset partitions different control and monitor points into registers, which are addressed using a request over an (typically RS485 twisted pair) asynchronous serial buss, as shown in Figure 3.1 (Ferris 1991).
Sensor Actuator Sensor Sensor

Dataset

Dataset

Antenna Control Computer
Ethernet to Control Building

RS-485 Bus

Figure 3.1: A diagram showing via the datasets to a serial buss, many implementations, a second buss on each dataset in order to dataset.

a typical dataset buss, with equipment connected and thence to the antenna control computer. In module, called an interface, connects to a parallel add extra control and monitor points to standard

Until now, these devices have been comprised of a double width AT module, approximately 480 x 220 x 70mm, containing an 8031 microcontroller and associated 7


8

CHAPTER 3: Dataset Engine

electronics, including a 12 bit Analogue to Digital Converter (ADC). The D3 version also included a multiplexer for the ADC. These devices are limited to a reasonably modest number of control and monitor points, and are also limited to 38.4kbps.

Figure 3.2: A photo of a "D2" dataset module. These units have provided sterling service to the Compact Array since their design in the 1980s. Parts for these modules are becoming increasingly scarce as they reach the end of their design life.

3.2

AT Dataset Proto col

In order to replace the standard dataset hardware, it is necessary to replicate at least a subset of the dataset protocol; the syntax and semantics for formulating dataset requests and responses. A common thread in discussions about the dataset protocol revolves around the suitability of the protocol for controlling CA antenna equipment. Before blindly duplicating the protocol, it is perhaps useful to analyse the requirements of the connection between equipment and ACC, lest a different scheme; for example Ethernet, is more suited to the task. The information transferred from the equipment is generally of a telemetry and diagnostic nature (Hall et al. 1992), for example: 1. Dewar temperatures, vacuums, and helium pressures, 2. LNA bias voltages, 3. System configuration commands, such as attenuator and switch settings, 4. Conversion chain power levels, used for setting gain. Across an entire antenna, there are of the order of 5,000 different control and monitor points. Many of these are entirely static, so need only be accessed infrequently. A subset (perhaps a few percent) are more important and are usually accessed every


CHAPTER 3: Dataset Engine

9

conversion cycle (approximately every ten seconds). A small number of points relate to rapidly varying values (for example Water Vapour Radiometer levels) and are read tens of times per second. The aggregate data rate is of the order of 1000 points per second. Given a 16 bit data word (two bytes) and protocol overhead of circa 50%, this results in around 30kbps data rate. So we may thus summarise the requirements for telemetry control and monitoring on Compact Array antennas: 1. Highly spatially dispersed equipment, typically with moderate to low complexity. 2. Moderate data rates, of tens of kbps. 3. High data integrity. 4. Extremely low RFI. 5. Low cost. 6. Serviceability. The RS485 buss is a useful standard on which to base the design, as it is simple and uses inexpensive twisted pair cable. Numerous robust industrial transceivers and modems are available which may drive an RS485 buss, at the modest data rates required by the application. Alternatives such as coax or twisted pair Ethernet prove unsuitable for the task, as they tend towards higher data rates (with concomitant higher levels of RFI) and Ethernet equipment tends to be more delicate and complex, being designed for data center use rather than industrial environments. However it should be mentioned that Ethernet is a clear choice in terms of implementation cost, being ubiquitous in the computer network field.

3.2.1

Request Format

Details of the inner workings of the dataset protocol are not widely published. In order to clarify the issue somewhat, this document summarises some of the information in (Ferris 1991), as well as points learnt from discussions with Mr Ferris. In order to communicate with a dataset, the buss master (typically the ACC) must compose a request packet, and transmit this packet over the buss. The request is sent bytewise in an asynchronous serial fashion. Information carried in the request packet is shown in Table 3.1. The Sync byte is used to signal the start of the dataset request packet. On reception of this byte (0x16) all datasets on the buss prepare to receive a dataset address byte. The Command/Monitor bit signifies the direction of data transfer, with a `1' signifying a command (data transfer from the ACC to the dataset). The Test bit is not normally used, and should be set to `1'.


10 Co de SYN CMD Spare DSA FN DATA

CHAPTER 3: Dataset Engine Description Sync Byte (designates start of request packet) Command/Monitor Bit Spare Bit (not used) Dataset Address Function Address Transferred data (0x0000 for monitor) Num. Bits 8 1 1 5 9 16 Value 0x16 0 - Monitor 1 - Control 1 0..31 0..511 0..65535

Table 3.1: Dataset request packet composition

The Dataset Address (DSA) is a five bit value denoting which dataset on the buss is being addressed. The length of this field sets an upper number of 32 datasets on any given buss. The Function Address (FN) is a nine bit value denoting the register that is being addressed within the dataset. The length of this field sets an upper limit of 512 registers within each dataset. The final two bytes of the dataset request packet contain either data in the case of a command, or else zeros in the case of a monitor request. Special Characters Request packets are sent as asynchronous serial data, with an eight bit byte, one stop bit, and odd parity. The Sync pattern (0x16) is treated as a special case. This pattern normally indicates the start of a packet. It is possible that this bit pattern will appear in normal data or address fields. To account for this special case, a system of escape codes is used to replace control characters in data and address bytes. in essence, an ESC character is sent, followed by a code describing the bit pattern of the substituted data. The details for the request packet are shown in Table 3.2. Co de ASCII `0' (0x30) ASCII `1' (0x31) Replaced Byte ESC (0x1b) SYN (0x16)

Table 3.2: Dataset request special characters

3.2.2

Resp onse Format

When a dataset is validly addressed, in that it receives a valid Sync, and then a DSA matching its own, it replies immediately with a response packet.


CHAPTER 3: Dataset Engine

11

Depending on whether the request is a command or monitor request, the dataset will respond differently. For a monitor request, the dataset replies with the contents of the addressed register, as shown in Table 3.3. Co de ACK DATA Description Acknowledge Byte (designates start of response packet) Transferred data Num. Bits 8 16

Table 3.3: Dataset monitor reply packet composition (no errors or warnings)

The dataset also replies to a command request, as verification that the dataset has received the data. In this case, the packet is of the form shown in Table 3.4. Co de ACK ERR WARN Description Acknowledge Byte (designates start of response packet) Contents of dataset error register Contents of dataset warning register Num. Bits 8 8 8

Table 3.4: Dataset command reply packet composition (no errors or warnings)

Error Resp onse In the case where a packet is received with an error, the dataset may reply with the ACK code substituted by an NAK. In this case the response is as for a command, and the contents of the error register are sent along with the NAK. The VHDL implementation makes use of only a small subset of possible error conditions, as many sources of errors, such as a watchdog timer timing out on the microcontroller version of the dataset, are not meaningful for a hardware based device. Table 3.5 shows all possible errors returned by the hardware dataset implementation: Error bit 0 1 2 3 4 5 6 7 Description Not used at present (always returned as `0') Parity or Framing error in function address or data Sync byte received when data expected Invalid escape sequence received in function address or data Not used at present (always returned as `0') Not used at present (always returned as `0') Not used at present (always returned as `0') Not used at present (always returned as `0')
Table 3.5: Dataset error register bit allocations

Note that the dataset only replies with an error if it is correctly addressed. Should the dataset receive a malformed Sync or DSA byte, it will simply flash an indicator on its front panel (if it has a front panel) and wait for a valid Sync.


12

CHAPTER 3: Dataset Engine

Thus the most common response to a problem, be it baud rate mismatch, data inversion, or other problem, is that the dataset does not reply to a request. In this case, the ACC must implement some form of time-out, so that it can report problems. Warning Resp onse The original dataset implementations had a number of conditions, such as a low backup battery, that would result in the dataset sending back a warning. In this case the dataset functions as normal, except it substitutes ACK bytes in each response with BEL bytes. Also the warning register (returned after each command request) will be set to some value depending on the nature of the problem. The VHDL implementation, being a simple hardware based device, has no conceivable state where it could respond with a warning. Hence the dataset will never issue a BEL, and the warning register will always be returned as `0x00'. Special Characters As for the request packet, several byte patterns are special, and are used as control characters. Table 3.6 shows each of these. Note that although warnings are never issued by the dataset, the BEL character is replaced by an escape sequence to maintain overall protocol compatibility with earlier units. Co de ASCII ASCII ASCII ASCII `0' `2' `3' `4' (0x30) (0x32) (0x33) (0x34) Replaced Byte ESC (0x1b) ACK (0x06) BEL (0x07) NAK (0x15)

Table 3.6: Dataset response special characters

3.2.3

Packet Padding and Resp onse Latencies

Due to the possibility of escape sequences in the request and reply packets, these packets are conceivably of variable length. If this were allowed, the possibility exists of a minimum length request packet being shorter than a maximum length response, leading to buss congestion and mangled response packets on heavily loaded busses. In order to avoid this problem, request packets are always padded with null (0x00) bytes, so that they have the same (maximum) length. The maximum request packet length would occur when the function address byte is an escape sequence, as well as both data bytes. This means that the ACC transmits an ACK, a DSA, and then a further six bytes, for a total of eight. In cases where this doesn't happen, the ACC must pad to at least eight bytes. The response time of the dataset is also an important figure. If datasets wait for variable times before they respond, then the possibility exists for a slow responding


CHAPTER 3: Dataset Engine dataset request. dressed. as soon

13

to still be using the buss when a fast dataset starts responding to a subsequent To avoid this possibility, the dataset must respond as soon as it is validly adOn the VHDL implementation, the dataset sends an ACK (or NAK) sequence as it recognises its own DSA.

3.2.4

Function Address Partitioning

Original datasets partition the control and monitor function address space (a total of 512 16 bit words) into a series of subsections, as indicated in Table 3.7 and Table 3.8 (Ferris 1997). Function Typ e Undefined Single Bit Data Addressed 8 Bit Addressed 16 Bit Decoded Addressed 8 Bit Decoded Addresses 16 Bit Reserved Undefined Word Undefined Base 0 64 96 160 224 228 232 236 256 260 Range 32 64 64 4 4 Index 0..31 0..31 0..63 0..3 0..3

4

0..3

Table 3.7: Control function address partitioning (D3)

Function Typ e Balanced Analog Unbalanced Analog Single Bit Data Addressed 8 Bit Addressed 16 Bit Decoded Addressed 8 Bit Decoded Addresses 16 Bit Reserved Undefined Word Undefined Multiplexed Analog Undefined

Base 0 8 64 96 160 224 228 232 236 256 260 288 352

Range 8 56 32 64 64 4 4

Index 0..7 0..55 0..31 0..31 0..63 0..3 0..3

4 64

0..3 0..63

Table 3.8: Monitor function address partitioning (D3)

The millimetre receiver contains some 512 analog monitor points. Unfortunately this does not fit within the prescribed multiplexed analog portion of the dataset function address space. Rather than have the millimetre receiver occupy eight dataset


14

CHAPTER 3: Dataset Engine

addresses (of a maximum of 32 on each buss) the decision was made to disregard the function address partitioning and treat all addresses within the function space as addressed 16 bit control and monitor points. Thus, for all function addresses, the dataset block generates a 9 bit address, and either transmits 16 bits of data, or receives 16 bits of data on its data buss. Should an application require the function addresses to be partitioned, this is easily accomplished by adding external logic to the dataset block.

3.2.5

Parallel Buss

The original dataset communicates with addressed devices via an eight bit buss. Sixteen bit transfers are made in two bytes, with a high/low signal to signify which half of the word is being controlled. In order to simplify the buss, the VHDL dataset engine uses simple sixteen bit transfers, and dispenses with the high/low signal. Should eight bit transfers be required, an additional state machine is available that interfaces an eight bit data buss to the 16 bit VHDL dataset buss. The timing relationships for the VHDL dataset are shown in Figure 3.3 and 3.4.
Address Write Stb Data 286us 286us 286us 286us

Figure 3.3: VHDL dataset parallel buss monitor read timing. Note that each of the time periods are dependant on the serial data rate. The example shown is for a 38.4kbps connection. Timings for other rates may be deduced by simply scaling the times shown.

3.3

VHDL Co ding

The new dataset engine was developed using Very high speed Hardware Description Language (VHDL). This language allows the description of complex digital hardware using a high level of abstraction and a relatively straightforward text based language. The language supports decision constructs, such as if..then, as well as case decision trees, and allows complex synchronous state machines to be designed simply, and with a high level of reliability and guaranteed metastability. In order to develop the dataset engine, the problem was split into two parts. Firstly, a simple Universal Asynchronous Receiver and Transmitter (UART) was designed, to


CHAPTER 3: Dataset Engine

15

Address Write Stb Data 286us 286us 286us 286us

Figure 3.4: VHDL dataset parallel buss control write timing. Note that each of the time periods are dependant on the serial data rate. The example shown is for a 38.4kbps connection. Timings for other rates may be deduced by simply scaling the times shown.

implement the eight bit, parity asynchronous communications layer with a minimum clock division overhead. Next, a layer was built on top containing the dataset protocol state machine, which decodes data from the UART according to the AT dataset protocol. Finally, a series of VHDL "test harnesses" were written in order to exercise the dataset engine under different conditions, and to test its response under a wide range of conditions, such as buss congestion and corrupted packets.

3.3.1

UART Design

Current datasets operate with either 38,400 bps or 4800 bps asynchronous serial data, with the parameters shown in table 3.9. Start Bits Data Bits Parity Stop Bits 1 8 Odd 1

Table 3.9: Dataset serial format

The VHDL dataset supports these standard rates, and also allows for higher data rates, dependant on clock rate. In order to minimise clock frequency, and thus keep RFI down, the UART design was carefully considered with a view to reducing the necessary number of clock cycles per bit. Start Detection To allow for errors in clock frequency between transmitter and receiver, it's important to start sampling data as close to the center of the start bit as possible. This is done by sampling the serial line eight times each bit. Whilst the receiver is waiting for a start


16

CHAPTER 3: Dataset Engine

bit, a running buffer is kept of the last four samples. The rest state for the serial input is a `1', so a start condition is defined as "0b1000" in the running buffer. When this pattern is recognised, the receiver then samples data every eight clocks thereafter. The samples are thus taken near the center of each bit time. The requirement for sensing three subsequent zeros also provides a degree of noise immunity to the receiver, as a short noise spike is unlikely to start it. Clock Divider The dataset is designed to operate with clock frequencies of nominally 1.2288MHz to 4.9152MHz. In order to translate this frequency to eight times the desired baudrate, a simple programmable divider is supplied, which will prescale the input clock by any integer from 1 to 16. A number of clock frequencies in this range divide neatly to standard baud rates, as shown in Table 3.10: Prescale 0000 0001 0010 0011 0101 0111 1011 1111 1.2288MHz 153.6Kbps 76.8Kbps 51.2Kbps 38.4Kbps 25.6Kbps 19.2Kbps 12.8Kbps 9.6Kbps 1.8432MHz 230.4Kbps 115.2Kbps 76.8Kbps 57.6Kbps 38.4Kbps 28.8Kbps 19.2Kbps 14.4Kbps 3.6864MHz 460.8Kbps 230.4Kbps 153.6Kbps 115.2Kbps 76.8Kbps 57.6Kbps 38.4Kbps 28.8Kbps 4.9152MHz 614.4Kbps 307.2Kbps 204.8Kbps 153.6Kbps 102.4Kbps 76.8Kbps 51.2Kbps 38.4Kbps

Table 3.10: Common baud rate dividers

For other clock frequencies and prescale values, the baudrate may be calculated using Equation 3.1. B audrate = fosc 8(P rescale + 1) (3.1)

The standard clock frequency is 3.6864MHz. This is a commonly available oscillator, and allows the same dataset to operate at 38.4Kbps (for compatibility on busses shared with D1 etc datasets) and also to run at up to 460Kbps, to allow for higher transfer rates. In order to minimise RFI, it is also possible to clock the dataset at just 307.2KHz, and have it operate on a 38.4Kbps buss.

3.3.2

Proto col Engine Design

In order to participate on a dataset buss, we need to be able to understand the protocol, from the point of view of the dataset.


CHAPTER 3: Dataset Engine

17

Like with the UART, the protocol engine is effectively split into a receive state machine and a transmit state machine. The receive state machine communicates with the transmit machine using the tx req variable, which triggers the transmit state machine to send either a monitor reply packet or an error reply packet. The receive engine makes use of the following states: 1. Idle: In this state the engine is waiting for the reception of an ACK from the UART. it should ignore all other data. 2. Receive DSA: Reception of an ACK while idle invariably leads to the receive DSA state. In this state we wait for the next byte from the UART, which should contain the dataset address, and command/monitor bit. Whether we pay attention to the rest of the packet depends on whether the dataset address received matches our own. Also note that the most significant bit of the function address is transmitted with this byte. This must be saved for future reference. 3. Receive Function: After the DSA byte, the next byte transmitted by the ACC is the function address. This address is simply copied out onto the address lines. 4. Receive Function after ESC: Should the receive function state receive an ESC, this state is triggered. The receiver simply reads the next byte, and decodes it accordingly. 5. Receive High Data: After receiving the function address, the request packet contains the high data byte for a command, or else nulls for a receive. 6. Receive High Data after ESC: Should the receive high data state receive an ESC, this state is triggered. The receiver simply reads the next byte, and decodes it accordingly. 7. Receive Low Data: The packet finishes with the low data byte, or else nulls for a monitor request. 8. Receive Low Data after ESC: Should the receive low data state receive an ESC, this state is triggered. The receiver simply reads the next byte, and decodes it accordingly. The protocol engine makes decisions in each state as to how to proceed with the transfer, and drives the transmit state machine accordingly. If a framing or parity error is received in the first two bytes, the engine ignores them and goes back to the idle state, waiting for the next SYN byte. Errors in subsequent bytes result in an error packet being requested, with the error flags set accordingly. The transmitter state machine makes use of the following states in order to send the reply packet: 1. Idle: The transmitter monitors the tx req variable. If tx req is send ack then the transmitter goes to the send ack state. If tx req is send err then the transmitter goes to the send err state.


18

CHAPTER 3: Dataset Engine

2. Send ACK: In this state the transmitter loads the UART with the ACK code, and then waits for the UART to signal that it is free before going to the send high state (for a monitor request) or the cmd err state (for a command request). 3. Send High: This state latches the high byte on the data buss and sends it. If the byte to be sent is a reserved code, it instead sends an ESC sequence and goes to the send high2 state, where the byte is sent, appropriately coded. 4. Send Low: This state latches the low byte on the data buss and sends it. If the byte to be sent is a reserved code, it instead sends an ESC sequence and goes to the send low2 state, where the byte is sent, appropriately coded. 5. Send NAK: The Send NAK state is triggered when a request is received with an error in the function address or data bytes. The transmitter must send an NAK code, as well as the err and warn registers, which are loaded according to the error. 6. Unload: Each of the error or ACK paths terminate with this state, which simply waits for the UART to unload before returning to the idle state. This ensures that packets do not become corrupted when, for example, a valid packet is received in the middle of an error reply.

3.3.3

Simulation and Testing

In order to faultfind operation of the dataset engine, a series of test harnesses were written for it, again in VHDL. These harnesses included simple commands to sequence through operations, such as supplying a valid request packet to the engine, then deliberately malformed packets, etc. while also simulating the operation of external devices connected to the dataset. When compiled and run, the simulation yielded a simple waveform trace, much like that found on a logic analyser, which could then be traced through in order to determine correct operation, or in the case of errors, used to track down the source of problems. Once the dataset engine was tested with a range of simulated data, it was then programmed into an interface card, and tested using a PC, with a simple dataset test program written in Labwindows/CVI. As implementations were developed using the engine, these too were tested, generally on test hardware, using a PC running the test software. Of interest here was the uncovering of a bug in the Labwindows serial communications routines, in that Labwindows (and perhaps Windows generally) ignores parity errors in received data, even when explicitly asked to report such errors via the serial drivers. This problem was uncovered because the dataset UART transmitter neglected to initialise its parity variable before each byte, so the parity of each byte was essentially random. Months of testing under Windows showed no problems whatsoever, but when


CHAPTER 3: Dataset Engine

19

Figure 3.5: A screendump of the waveform output from a simulation of the VHDL dataset. In this case the dataset is being tested along with additional code to transfer eight bit items.

the interface cards were run under a Linux test system, parity errors abounded. Careful inspection of logic analyser output illuminated the problem.

3.4

Schematic Instantiation

In order to make use of the dataset engine within schematic based designs, it was necessary to build a Protel schematic component representing the dataset block.
U17
RXD TXD TXD_EN ADD< ADD< ADD< ADD< ADD< ADD< ADD< ADD< ADD< 0 1 2 3 4 5 6 7 8 > > > > > > > > >

PAR ERR

WR STB DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15>

CLK DSA< DSA< DSA< DSA< DSA< 0 1 2 3 4 > > > > > 0 1 2 3 > > > >

BAUD< BAUD< BAUD< BAUD<

RST

DATASET

Figure 3.6: The dataset schematic symbol. Pins on this symbol are related to the VHDL dataset entity description.

The VHDL entity description provides information about how the component connects to the outside world, such as the naming and type of all signals. It is thus a


20

CHAPTER 3: Dataset Engine

simple task to create a Protel schematic component with identical pins, and ensure that the Xilinx compiler maps the correct netlist file when reading the design.

3.5

Summary

The ATNF has no previous experience with VHDL models, either for use in simulation only or as synthesisable cores. The dataset engine synthesisable core, whilst useful in its own right as a control structure for embedded equipment, has also provided a thorough grounding in the use of VHDL both in a stand-alone sense, and combined with a schematic entry process, such as is typically used at the ATNF. The same development process used for creating the dataset engine has since been applied to a number of other digital pro jects, such as ADC sequencers, cross-point switch units, and has more recently been proposed for use in digital correlator designs.


Chapter 4 Receiver Interfaces
This is the rock-solid principle on which the whole of the Corporations [IBMs] Galaxy-wide success is founded...their fundamental design flaws are completely hidden by their superficial design flaws. T.H. Nelson

4.1

General Interfacing Requirements

The millimetre receiver package is actually three receivers sharing a common dewar. As such, a large number of control and monitor points are required. In order to reduce the likelihood of interference between different receiver subsystems, and also to reduce the size of wiring bundles on the receiver package, the interfacing task is subdivided into a number of different parts, namely: · Electronics cage, providing control and monitor of dewar parameters (vacuum, cryogenic temperatures, helium pressure, etc.), LNA bias voltages and currents, power supplies, and translator control and monitoring, · Water Vapour Radiometer, providing monitoring of the four water vapour channel power levels, as well as total received power, · Conversion system, providing monitoring of RF levels through the conversion chain, as well as configuration of various microwave switches and attenuators, to set the IF bandwidth and levels, · Local oscillator system, providing monitoring of the 160MHz local oscillator reference, the optical reference, and the local oscillator power, as well as control the YIG oscillator control word. These interfaces communicate with one another via an RS485 buss, carried on the electronics cage backplane, and via cables to the conversion enclosure and water vapour radiometer. The main electronics cage interface, designated the "F83", in addition to performing its own interface functions, also acts as a fibre modem, allowing all electronics on the receiver package to be controlled and monitored via a simple fibre pair. 21


22

CHAPTER 4: Receiver Interface

4.2

F83 Interface

The F83 interface is used for control and monitor of power supplies, LNA bias supplies, and dewar cryogenic data, including cryogenic temperatures, helium supply and return pressures, and dewar vacuum, as well as providing control for the translator, which drives different feeds onto the telescope axis. Previous receivers made use of an "F33 Dataset Interface" card, which contained a number of simple latches and buffers, allowing a D2 dataset, connected via a parallel address and data buss, to control various functions within the receiver electronics cage. A number of other cards are standard on AT receivers to do such things as multiplex bias monitor points and condition the vacuum sensor signals, etc.

Figure 4.1: A picture showing the F83 interface card, along with its RFI covers. The fibre interfaces are toward the top of the picture, whilst the DIN91216 connector is toward the bottom. In operation, the RFI covers are bolted either side of the PCB, forming a sandwich.

In order to allow retrofitting of older receiver designs, the F83 is designed to have a modicum of backward compatibility with the previous F33 + D2 dataset combination that drives most AT receivers.

4.2.1

RFI Mitigation

Radio astronomy receivers are carefully designed to maximise receiver sensitivity within their operating band. Whilst these receivers are coupled to large feedhorns, in order to couple energy efficiently from the antenna system, sidelobes mean that the receiver is susceptible to radiated fields within the vertex room. In order to minimise pickup of Radio Frequency Interference (RFI) from electronic equipment, it is customary to isolate all clocked components, such as datasets, samplers, and the like on a separate floor, with shielding in between. Further, digital signals controlling the receivers are usually static during the active part of a conversion cycle. The F83 card introduces a 3.6864MHz oscillator into the same room as the microwave feeds. This oscillator is necessary for recovering data from the dataset asynchronous serial stream. It is imperative to ensure that RFI from this oscillator is at a low enough level that it does not interfere with observing.


CHAPTER 4: Receiver Interface

23

The worst case scenario for RFI on the Compact Array involves the L-band receiver. This receiver operates down to 1.2GHz. The system temperature of the receiver system (at 1.5GHz, and neglecting contributions from the cosmic background, the atmosphere, and the antenna structure) is approximately 21K (Sinclair et al. 1992). Equation 4.1 (Christiansen and HЁ om 1969) provides a means to convert this value to a detection ogb threshold: Tsys (T ) = QM v t (4.1)

Substituting an arbitrary value of 1 for Q (information factor) and 1 for M (ideal receiver), and using a typical channel bandwidth (v ) of 64KHz (64MHz IF, 1000 channels) over a 12 hour integration, gives a sensitivity threshold of some 3.2 в10-4 K . This is expressed as a power using the following relationship: P (dB m) = 10log (1000k B T ) (4.2)

Where k is Boltzmans constant (1.38 в 10-23 ), B is bandwidth (64KHz) and T is temperature. This comes out to some -185dBm. Such a figure should be taken with a grain of salt, as it does not take into account the complex losses between the interference source and the feed (instead assuming perfect coupling), and also neglects the correlation isolation for such signals afforded by the phased array. However it still provides some feel for the signal levels which may be detected by the receiver. In order to keep radiated signals from the interface equipment to these low levels, a number of strategies were employed to reduce emissions originating from the oscillator. These were: · Using as low a clock rate as practicable. This is facilitated by the VHDL UART design, which has a в8 clock, rather than the more usual в16 clock of microcontrollers. · Ensuring clock trace lengths were kept to a bare minimum, to minimise radiation. · Using lossy ferrite "T" filters on clock and oscillator power. · Pouring solid ground planes on all board layers, to minimise RFI coupling between traces. · Manufacturing a bolt on RFI shield for the PCB. · Passing all I/O and power traces through lossy ferrite filters at the point where they cross the RFI shield.


24

CHAPTER 4: Receiver Interface

4.2.2

PCB Design

The Printed Circuit Boards (PCBs) for the F83 interface were designed using Protel Schematic and Protel PCB. These packages communicate with one another via netlists. This software is part of the standard design suite used at the AT. In order to reduce overall cost, a two layer design was used, with 7 thou (0.18mm) minimum track width and separation, and 20 thou (0.5mm) minimum hole diameter. These design rules allow the use of inexpensive local manufacturing services, and do not generally require the use of bare board testing. In order to make the most use of the reconfigurability of the Xilinx FPGA, the schematic was modified to make the PCB layout as clean as possible. The PCB conforms to DIN "Eurocard" standards. All I/O is either via a 128 way DIN91216 connector to the receiver backplane, or via the fibre interface on the front of the card. The PCB is shown in Figure 4.1 Analog to Digital Conversion The Analog to Digital Converter (ADC) posed some interesting design challenges, inasmuch as the original F33 card, which the F83 was supposed to provide backwards compatibility with, had only a +5V supply, yet afforded an analog signal range of ±5V.
VCC +5V

U21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 VIN AGND1 REF CAP AGND2 D15(MSB) D14 D13 D12 D11 D10 D9 D8 DGND VDIG VANA BUSY CS R/C BYTE D0 D1 D2 D3 D4 D5 D6 D7 28 27 26 25 24 23 22 21 20 19 18 17 16 15

ANALOG IN

R1 200R 0.1% D2 BZV55C4V3

R2 33K2 0.1% C1 4n7 C4 2u2 C2 2u2

D3 BZV55C4V3

AnBSY AnEN AnST HIGH D0 D1 D2 D3 D4 D5 D6 D7

C39 10uF

C42 10uF

LTC1605-2CG

Figure 4.2: The F83 ADC schematic. The ADC chip is able to digitise a ±4.096V range, despite being powered by +5V.

A design using a DC-DC converter was considered, but rejected due to concerns that the supply would generate excessive RFI. Instead, a 16 bit single supply ADC (Linear Technologies 1999) was utilised, which uses a novel switched capacitor input stage to enable it to handle a ±4.096V input. In order to ensure that the ADC can keep up with the dataset engine, without introducing delays that may cause conflict between buss devices, it's necessary to look at the time available in the protocol for returning data. On reception of a valid request Dataset and Function Address, the dataset engine then replies immediately with an ACK byte, and then the upper and lower eight bits of the monitor point. The upper eight bits of the ADC result must be valid at the end of the ACK byte, ten bit times after the function address is valid. At 38.4Kbps (the upper speed used by the AT standard datasets) this corresponds to 260µs. The ADC used is self clocking, and performs a conversion in just 10µsec


CHAPTER 4: Receiver Interface

25

(100Ksps). This implies an upper dataset buss limit of approximately 1Mbps, which is ample for current and future requirements. Careful attention to detail was observed with the ADC board layout, to ensure that digital signals would not degrade the noise performance of the ADC. The ADC power supply was bypassed with a 100µH inductor, and a series of 10µF ceramic capacitors. These ceramic capacitors were chosen for their extremely low ESR and small size when compared with similar value tantalum or electrolytic capacitors. Digital I/O The F83 card provides some 108 individual TTL level digital I/O lines. Each line is individually driven by a Xilinx pin, for maximum flexibility in design. The digital lines from the interface travel on a receiver backplane, with a distance between transmitter and receiver of as much as a metre. Whilst high speed operation is not important, low RFI contribution is a serious concern, as is current drive for expected loads of up to ten TTL gates. A high level of noise immunity is also desirable. Digital I/O from the interface is buffered using 74ACTHQ series buss transceivers. These devices are well suited to the application, as they have slew rate limited drivers, and 25 series resistors to minimise ground bounce and RFI. In addition, they make use of a "keeper circuit" which holds receiver inputs at their current level with a weak current, to improve the noise immunity. In this way, it's possible to build the card without pullups on the digital inputs, which would otherwise be difficult and tedious to fit on the board. Xilinx Configuration The program for Xilinx FPGAs is stored off-chip in a programmable memory device, which must be programmed before the interface is used. In order to simplify the development process, an Atmel EEPROM device was used, which is simply reprogrammed in circuit using a short cable from between the programming board and a header on the interface card. The prototype interface located the programming header outside the RFI shield, but the RFI filters played havoc with configuration signals, so it was decided to relocate the header under the shield, necessitating the removal of the shield to reprogram the card. Fibre and Twisted Pair I/O The F83 interface is the boundary point between the external (fibre optic) dataset buss, and the internal (twisted pair) dataset buss. In order to facilitate the F83s role as a fibre modem, the interface card has both RS485 twisted pair drivers and optical fibre transceivers. Signals for each are derived from the FPGA, for increased flexibility in use. This means that, for example, F83 cards may be programmed as slaves on the twisted pair buss, rather than driving it. This functionality was used in the Taiwanese AMiBA (AMiBA 2002) prototype receiver, where extra I/O was desired.


26

CHAPTER 4: Receiver Interface

The twisted pair interfaces make use of Maxim MAX487 RS485 transceivers. These devices use low input current receivers (enabling up to 128 devices on a buss) and slew rate limited transmitters, which operate with reduced RFI at up to 250Kbps. The fibre interfaces are based on a Diamond E2000 duplex fibre pair, which utilise Honeywell HFE4047 fibre emitters and HFD3023 schmidt trigger PIN detectors. The detector specifications are summarised in Table 4.2, whilst those of the transmitter are in Table 4.1. Link budget calculations for the link are shown in Table 4.3, using the transmitted power, receiver sensitivity, and nominal values for loss of various interconnections. Coupled Power Drive Current Peak Wavelength Bandwidth -17dBm (into 50/125µm fibre 50mA 850nm 100MHz

Table 4.1: HFE4074 fibre transmitter specifications summary

Sensitivity Min. Dynamic Range Peak Wavelength Max. Data Rate

-27dBm (from 50/125µm fibre 15dB 850nm 5Mbps

Table 4.2: HFD3023 fibre receiver specifications summary

Transmit power ACC to pedestal bulkhead fibre (0.01km @ 2dB/km) Pedestal bulkhead connector Pedestal fibre splice Fibre through az. and el. wraps (0.2km @ 2dB/km) Sampler rack fibre splice Sampler rack bulkhead connector Sampler rack to receiver fibre (0.01km @ 2dB/km) Power at receiver Noise margin

-17dBm 0.02dB 0.30dB 0.10dB 0.40dB 0.10dB 0.30dB 0.02 -18.24dBm 8.76dB

Table 4.3: Compact Array receiver interface fibre link budget

4.2.3

FPGA Design

The F83 interface card is mainly a programmable logic design. In order to communicate with the antenna control computer, it includes a dataset engine, which controls other logic within the FPGA via a simple parallel buss.


CHAPTER 4: Receiver Interface

27

Addresses from the dataset engine are decoded, and a variety of registers are accessed to control receiver systems. One of the primary functions of the F83 is as a monitoring point for LNA bias and dewar environmental parameters, such as vacuum, temperature, etc. These variables are read in analog form, and are multiplexed via a series of bias mux and analog mux cards in the receiver electronics cage. In order to perform a conversion when needed, the F83 contains a simple ADC sequencer, which sets up the analog multiplexer addressed, and then initiates an ADC conversion after a settling period. The sequencer then monitors the ADC ready/busy line, waiting for the conversion to finish, and finally transfers the data in two bytes from the ADC to the dataset parallel buss. This logic, being based on a simple state machine, is written in VHDL. A similar model was also written to read the ADC, and then scale and offset the result to a 12 bit number, as per the D2 specification. This design was used along with a simplified buss driver to "emulate" a D2 dataset + F33 interface combination, as used in the multibeam receiver, as well as other previous AT receivers. This allowed RFI problems caused by the proximity of the multibeam to its D2 dataset to be alleviated.

4.3

Conversion Interface

The conversion interface is used to control switches and attenuators within the downconversion system (Graves et al. 2002), and to monitor signal and local oscillator levels within the conversion system. This interface was originally intended to also control the local oscillator module, but in order to minimise connections to the local oscillator module, the local oscillator instead has its own dedicated interface, which is detailed later. Due to fears of local oscillator leakage from the conversion system, the entire system is sealed up within an RFI shield, and is controlled with just two twisted pairs, plus an event pair. As with the F83 interface, the conversion interface controls switches and attenuators etc. via a number of TTL level digital lines. Unlike the F83, all analog multiplexer functions for monitoring signal levels must be done by the interface.

4.3.1

PCB Design

Many of the same design constraints that applied to the F83 interface are also pertinent with the conversion interface. Some elements of the design, for example RFI mitigation, were somewhat relaxed however, as the entire conversion module is enclosed in an RFI shield, with filtered feedthroughs used for all signal and power connectons. Space constraints on the conversion module led to the use of a four layer board, with 7 thou design rules for the interface. Much of the PCB real estate is occupied by connectors.


28

CHAPTER 4: Receiver Interface

Figure 4.3: A picture showing the millimetre conversion interface card. The PCB size is dictated largely by the connectors used to get signals and power on and off the board. Note that this card does not have the strict RFI requirements of the F83, and thus does away with the RFI covers and filters.

Whilst there was no need to add RFI shielding to the interface, attention was still paid to minimising possibility for interfering fields being coupled off the board. As with the F83 interface, this centered around the oscillator, and its connection to the FPGA. This net was kept short, and solid ground planes were provided around and under the oscillator and FPGA so that fields would preferentially couple to the planes. Analog to Digital Conversion The detector signal conditioning circuits used for the conversion system use differential signals. In order to accommodate these signals, the analog multiplexer was doubled up, and a differential to single ended converter was used before the ADC. This improves the noise immunity of the sampler, because coupled common mode noise is rejected by the differential amplifier. Otherwise, the ADC setup is the same as that used on the F83 interface.

4.4

Lo cal Oscillator Interface

The local oscillator interface is responsible for control and monitoring of the L86 local oscillator module. This module was originally intended to be controlled by the conversion interface, but concerns over possible intermediate local oscillator frequencies leaking from the enclosure led to the design of a separate local oscillator interface, in order to minimise wiring to this module. The local oscillator module is comprised of a number of parts, including a fibre receiver, with a power detector, and a PLL driven YIG oscillator, which is locked to


CHAPTER 4: Receiver Interface

29

Figure 4.4: A picture showing the local oscillator interface card. This card fits alongside the local oscillator phase locked loop module, hence the odd shape. As with the conversion interface, RFI is not a great concern, so the card has no covers and no RFI filtering.

the fibre reference. The YIG frequency depends on a 12 bit digital control word, which is supplied by the interface. In addition, the YIG coil current is monitored, so that a simple under/over comparison may be made to determine if the oscillator is likely to lose lock.

4.4.1

PCB Design and Packaging Issues

The design of the local oscillator interface follows closely that of the F83 and conversion interfaces. RFI shielding is not as important for this module, as it is enclosed within the L86 module, which is heavily shielded in order to keep local oscillator signals from escaping. However, the same design techniques as used on the F83 board, such as locating the clock chip close to the FPGA, and minimising clock trace length, have also been employed on this board. The primary challenge in the design of the local oscillator interface was one of packaging it so that it would add a minimum of size to the L86 module. A four layer board was designed to accommodate the Xilinx chip, config PROM, ADC, some muxes, and power supply electronics in a scant 15cm2 . Indeed the ma jority of space on the PCB is occupied by two connectors, via which it communicates with the L86 and the outside world.

4.5

Water Vap our Radiometer

The Water Vapour Radiometer (WVR) (Abbott and Hall 1999) is an experimental system intended to increase the upper frequency limit of the Compact Array under less than ideal seeing conditions. The placement of the Compact Array, in Northwestern NSW, whilst being close to optimum for centimetre wave observing, is too low in altitude and high in humidity for good year round millimetre observing. Water vapour has a higher dielectric constant than dry air, having the effect of delaying microwave and millimetre wave signals (as well as attenuating them except in certain bands). In areas of relatively high humidity, the density of water vapour in a given column of atmosphere varies markedly from place to place. The result with a synthesis telescope is decorrelation, and subsequent loss of signal, at higher frequencies.


30

CHAPTER 4: Receiver Interface

By accurately measuring the density of water vapour in the beam for each antenna, it is hoped that the phase shift on the astronomical signal introduced by the water vapour can be cancelled out by the correlator, thus improving the system tolerance to atmospheric water vapour. The method used in the millimetre receiver to measure water vapour consists of a simple offset feed, with a low noise amplifier, followed by four simple TRF receivers, centered on different bands around 26GHz. The signal level in these bands approximate the density of water vapour within the received beam. The WVR interface thus digitizes the output of each of the detectors, along with a number of other parameters that may affect the system, such as LNA temperature and feed temperature.

4.5.1

PCB Design

The PCB design methodology adopted for this interface was as for the F83. As with the F83, great care was exercised to ensure that RFI, predominantly from the oscillator, was not carried outside the enclosure. To these ends, all signals in and out of the interface are filtered with RFI suppression filters, and a tight fitting RFI shield was designed and fabricated.

Figure 4.5: The interface card for the Water Vapour Radiometer.

The WVR interface connects to the receiver via a simple 9 pin D connector. Power (±20V) and all other signals are carried on a 2 row DIN connector. The WVR assembly was originally designed with the intention that the analog signals (±10V differential) would be carried on a cable to the main receiver backplane. However, tests showed that the 16 bit ADC on the receiver electronics package wasn't up to the task. In order to avoid a costly redesign of the WVR package, the interface board was designed to fit within the enclosure, above the WVR power supply board.


CHAPTER 4: Receiver Interface Analogue to Digital Conversion

31

Initial system tests using a National Instruments 16 bit data acquisition card indicated that the quantization noise in this system was a ma jor contributor to total system noise. Thus, in order to ensure that quantization errors did not adversely effect performance, the digitizer was specified with a minimum SNR of 90dB, or 15 bits. This specification, when teamed up with the requirement to sample all channels in under 100 milliseconds and the need for high levels of long term system stability, proved a daunting challenge. A survey of available ADCs revealed that most 16 bit chips only guaranteed typically 14.5 effective bits SNR. In order to guarantee 15 bits SNR, a 24 bit delta-sigma ADC chip was chosen as the core of the design. This device, an ADS1252 (Texas Instruments 2000), guarantees 18.6 bits effective resolution over temperature, at a sample rate of some 40Ksps. It was important when designing the ADC signal conditioning circuitry (shown in Figure 4.6) that the SNR specifications not be compromised by noisy input switches and op-amps. Similarly, variations with temperature were to be minimised, in order to reduce the effect of the periodic air-conditioner cycle on the system.
+15V

1

U16
EN 17 16 15 19 20 21 22 23 24 25 26 11 10 9 8 7 6 5 4 A0 A1 A2 N1A N2 N3 N4 N5 A A A A COMA 28

V+

MUX_A_EN MUX_A0 MUX_A1 MUX_A2 ANI0+ ANI1+ ANI2+ ANI3+ ANI4+ ANI5+ ANI6+ ANI7+ ANI0ANI1ANI2ANI3ANI4ANI5ANI6ANI7-

18

+15V

C32
+15V +5V

100n 25V
7

U18 AD620
2 6

7

8

AN+

2 1

U21
6 1 +VIN 3 2 -VIN

3

U22
+VD D
4 CLK DOUT 5 6 SC LK

R6 30K1 0. 1%

ADC_CLK ADC_DOUT ADC_SCLK

8

N6A N7A N8A 2 N1 N2 N3 N4 N5 N6 N7 N8 B B B B B B B B COMB

AN-

3

8 VR EF

C33 2V5REF 100n 25V
- 15V +15V

GN D

C31 U20 MAX307CWI 470n 25V C21 1u 10V
2 VIN VOU T 3 NR 5 TR IM GN D 6

27

V-

12

- 15V

4

C29 3u3 10V

MAX6325

Figure 4.6: A schematic diagram showing the signal conditioning circuitry, ADC, and associated reference for the WVR. Note that this figure is slightly inaccurate, as it omits the second multiplexer, but is adequate to illustrate the design principles used.

The analog inputs are thus multiplexed with a pair of MAX307 differential 8 to 1 multiplexers. These use low on-resistance switches, of just 60, minimising additional noise contribution by series resistors in the input stage. The selected signal then passes through an AD620 differential amplifier, to convert to a single ended signal centred around +2.5V. The AD620 has a low input noise of 70nv/ Hz (Gain = 1), as well as an input bias current of 1nA. When combined

7

C20 100n

GN D

OP-177
4 1

4

5

ADS1252
- 15V R7 10K0 0. 1%


32

CHAPTER 4: Receiver Interface

with the MAX307 input resistance, the noise contribution is approx 3µV pk-pk (0.1 to 10Hz). This equates to around 22 bits, or 8 LSB. The signal is next divided by four by a simple voltage divider, in order to scale it to the correct ADC range, and buffered by an OP177 precision low noise op-amp, before being input to the ADC. The OP177 maintains the low noise levels of the differential amp. The voltage reference is based around a MAX6325 precision reference, with 3ppm accuracy over temperature. The MAX6325 offers access to the reference element, so that noise may be reduced by the use of a large value capacitor (in this case a 1µF ceramic). Of course, it is necessary to follow strict layout guidelines in order to preserve the specs of these components, paying particular attention to the separation of analogue and digital ground planes on the board, and ensuring that no traces cross the planes to couple digital noise into the analogue subsystem. The result, as shown in Figure 4.7 is an impressive quantisation SNR of 110dB, or 18.5 effective bits.

Figure 4.7: A histogram showing the distribution of samples from the 24 bit WVR ADC, when recording data from a precision 50mV reference. Each bin is 80 µV or 67 ADC counts. The standard deviation of this data is 24 µV (110dB SNR)

4.5.2

FPGA Design

The main additional component required in this interface was a sequencer for the analog to digital converter. A serious issue in the design of the sequencer is that the ADC is far too slow to perform a conversion during a normal dataset request-response interval. In addition, the 24 bit data returned by the ADC will not fit into a 16 bit dataset register. Further, the ADC has no "conversion start" command.


CHAPTER 4: Receiver Interface

33

The solution to these problems lay in continually reading all analog inputs one after the other, and storing the results in temporary registers, which may be read as desired. This method has the drawback of introducing a measure of indeterminacy in the timing of the sample, as well as consuming a considerable amount of Xilinx resources for the registers necessary. The timing jitter turns out not to be a serious concern, as it is masked to some extent by software timing jitter in any case, and by significant filtering on the sampled data, both before the interface, and in software post-processing. The sequencer is designed in VHDL, and is a simple state machine, composed of a counter which drives the multiplexer to select one of the eight inputs, and a clock generator for the ADC, which clocks the converter at 1/6th of the crystal frequency (614.4KHz). For each input, eight successive conversions are performed. All but the last are discarded. This is necessary because the ADC contains digital FIR filters, which are six conversions long. When a step input is applied, as with switching from one voltage to another, six conversions are necessary before the ADC settles down. The result is that the sequencer updates all eight registers once every 20msec. This rate was not chosen by accident, but rather gives a high degree of 50Hz mains frequency rejection to the system. The final part of the design is a simple shift register to reconstruct the serial output of the ADC into a parallel form. When reading a 24 bit register, a scheme was developed to allow 24 bit reads while ensuring that the high and low order data was always from the same conversion. The high order 16 bits are read first by a dataset monitor request. Concurrently with the read, the low eight bits from the relevant register are placed in a temporary register, which may then be read at a different address. In this way, the converter may be treated as an accurate 16 bit converter in one read, or as a 24 bit converter in two.

4.6

Testing

In order to simplify testing of these various interfaces, they were tested in a number of different ways at various points in their development to ensure that they worked as expected. As a rule, the FPGA design paralleled that of the physical interface boards. Elements of the FPGA designs, such as the dataset engines and various ADC sequencers, were simulated stand alone using a VHDL synthesis package, before any hardware was built. Whilst designing the PCBs, design checks were made both during schematic development, and during board design. In the case of the schematic design rule check, the test flagged such items as: · Multiple outputs driving a common net. · Unconnected inputs, or nets with no source.


34 · Unconnected power nets. · Duplicated designators etc.

CHAPTER 4: Receiver Interface

Whilst these tests are by no means exhaustive, they give some idea that the schematic is a true representation of the design. Next, as a final stage in PCB design, a second design rule check was run on the PCB design. This check tested the PCB against the loaded netlist, and flagged errors such as: · Footprint mismatches between PCB and schematic. · Unrouted or partially routed nets. · Clearance violations and shorts between nets. · Track widths not within design rules. Of course the creation of a reasonable PCB layout depends heavily on generating workable, sensible design rules for features, such as signal and power net track widths, clearance constraints, via size, etc. Finally, once the prototype boards were constructed, they were powered up and programmed, and then test software was loaded into the FPGAs to exercise their various functions.

Figure 4.8: The F83 interface test board, which proved an invaluable tool for chasing PCB soldering problems amongst the thousand of soldered connections on each F83 interface.

One area that proved troublesome was the RFI filters on the F83 cards, which were difficult to solder, resulting in a large number of dry joints or bridged pins and subsequent frustration. In order to effectively and quickly test the digital I/O lines on the F83 cards, a test board was built, which the F83 plugged into. This board


CHAPTER 4: Receiver Interface

35

contained an LED for each digital I/O line. Test software was loaded into the F83 card which simply displayed a moving bar on the LEDs, making shorts and opens very obvious because of disruptions in the LED pattern. As RFI emanations were identified in the design specifications as a ma jor concern, the F83 card was also tested extensively to ensure that the RFI levels were within acceptable limits. The RFI performance was measured on a prototype F83 card, with RFI covers in place, and using a 1.2288MHz oscillator as a timing reference. The emitted field was sampled at a distance of 2cm from the backplane connector, using a broadband Rhode & Schwartz E-Field probe, and wideband LNA (100KHz-2GHz, 30dB gain, 3.5dB noise figure). The test setup (with an unshielded card) is shown in figure 4.9.

Figure 4.9: The F83 interface, being tested for RFI emissions, using an E field probe, LNA, and spectrum analyser.

The results of the RFI testing were extremely encouraging. Whilst it was possible to find evidence of the oscillator harmonics, they were down in the spectrum analyser noise, and required considerable work to display, with long sweep times. The results are shown in Figure 4.10 for three frequencies; 480MHz, 960MHz, and 1.44GHz. Emissions are around -125dBm below 1GHz, and drop to around -140dBm at 1.4GHz. Whilst this is considerably more than the minimum detectable signal at 1.4GHz, this is unlikely to cause problems unless the interface is placed within the primary beam of the telescope. Of course, the final proof of operation of any device is in actual use. The final stage of testing was to install the interfaces on prototype receivers and then to test the receiver interfacing as a whole. To facilitate this effort, a number of programs were written, as detailed in Chapter 5.


36

CHAPTER 4: Receiver Interface

Figure 4.10: Test plots from the F83 interface, with a 1.2288MHz oscillator and RFI covers fitted.


CHAPTER 4: Receiver Interface

37

4.7

Summary

This chapter describes the design and construction of a number of different implementations of the dataset engine in hardware form. Each interface unit makes use of programmable logic to house the engine, as well as other logic, and has peripherals attached to add additional functionality. In designing the F83 interface, careful attention was paid to minimising radiated fields, so that it does not interfere with observing processes. It was also designed in such a way that it provided an upgrade to existing receivers. The WVR interface data acquisition circuit proved challenging to implement, in order to minimise noise on the analog inputs. The result of this careful design was an acquisition system with some 18.5 bits of effective resolution, more than enough to ensure that quantisation noise was an insignificant contributor to overall WVR system noise. The local oscillator and conversion interfaces show just how small the interface hardware can be made using multi-layer circuit boards and fine pitch SMT parts, and provide a glimpse of the future directions the interfacing effort will take in the AT; one of reducing the number of control wires in systems by locating small, cheap interfaces close to the sources of data. Each of these implementations follow a similar design process, whereby the system is partitioned into manageable modules, and then the I/O requirements of each module are identified, and an interface designed to suit. Testing is done in each case first on a simulator, for VHDL components, then with specially constructed test jigs for prototype hardware, and finally on the actual receiver system.


38

CHAPTER 4: Receiver Interface


Chapter 5 Test Software
C is often described, with a mixture of fondness and disdain varying according to the speaker, as "a language that combines all the elegance and power of assembly language with all the readability and maintainability of assembly language". MIT Jargon Dictionary

5.1

Overall Requirements

The code developed as part of this pro ject was done so more for diagnostic and testing processes than for final use. A large software suite already exists to control observations with the Compact Array, and in routine use, it is anticipated that this software will also encompass the hardware described in Chapter 4. That being said, however, two important points led to the need to develop some semblance of control and monitoring software which is independent of the main online code. These are speed of development, and the need for an independent "arbiter" of system functionality. This last point is brought about by the concurrent upgrade of antanna control computers, from LSI-11 based systems to industrial PC machines running the pSOS real time operating system. It was felt that some rudimentary independent driving software for the receivers would be helpful in diagnosing both receiver hardware and ACC software problems. The language used for development of this code was National Instruments Labwindows/CVI (National Instruments 1996). This language was chosen for the following reasons: 1. We already owned a copy, and I was proficient in its use, 2. The languages' C base meant we could use pre-existing dataset drivers, 3. The language includes a range of useful instrumentation GUI "widgets" which would simplify development of control panels, etc. 39


40

CHAPTER 5: Test Software

4. Unlike its close cousin, Labview, Labwindows/CVI code is compiled, and runs at reasonable speed on modest hardware.

5.2

Dataset Libraries

As stated previously, existing dataset libraries were used as the basis for much of the test software. These libraries have been developed over the last fifteen years or so in order to allow control of equipment connected to the usual "D1", "D2" etc datasets. Whilst the VHDL "dataset engine" was designed as a software compatible replacement of the older datasets, due to differences in implementations, some thought was still needed in the use of the libraries. The best example is the way original dataset functional address space was partitioned into ranges, for example "16 bit addressed" range etc. The libraries are based on this partitioning, and contain functions of the following form: int Addressed_8_Bit_Out(int ds_address, int control_point,int data_out) which allow access to the relevant subset of the functional address, and perform meaningful bit masking etc. on data transferred. While the possibility exists of building additional logic around the dataset engine to implement these ranges (as indeed was done in the multibeam dataset replacement), by and large the ranges are dispensed with. This means that the most useful functions in the dataset libraries are the slightly lower level "Initialise_Dataset" (used to open the comm port), "SendMessage" (which formats a request and sends it on the selected comm port), "ReadResponse" (waits for a response to arrive and decodes it), as well as "Close_All_Datasets". Using these functions, the system may be thoroughly tested.

5.3

Dataset Test Co de

The dataset test panel was the first program written for debugging the dataset connection, during development of the dataset engine. This code has been revisited numerous times, as different problems were encountered with the interface hardware, in order to make it display more meaningful information about the link.

Figure 5.1: A screendump showing the dataset test panel. The last two attempts at communication were unsuccessful, as shown in the history display.


CHAPTER 5: Test Software

41

This code presents the user with a simple control panel (shown in Figure 5.1), in which dataset transactions may be made, and the results displayed. The user is able to set comm ports and baud rates with pull down menus. In order to debug remote TCP/IP connected systems, a version even exists whereby the server is run on the machine connected to the dataset buss, then a client is able to drive the server, and thus exercise the buss.

5.4

Receiver Monitor Panel

The receiver monitor panel is a large diagnostic utility, which displays many of the analog monitor points on a receiver, including such things as low noise amplifier bias conditions for every stage on every amplifier, dewar parameters, power supplies, etc. This is a large amount of information, so a selection must be made via a simple pulldown menu as to which band is being monitored at a given time. The user interface panel is shown in Figure 5.2.

Figure 5.2: A screendump showing the millimetre receiver monitor panel. The panel is displaying actual telemetry, in this case from the receiver in CA02.

Considerable difficulty was encountered with this program in ensuring its responsiveness to the user interface. The program spends most of its time I/O blocked waiting for responses from dataset requests, and is able to respond to the user only occasionally. If a problem occurs, such as a non-responsive buss, the program would all but hang, waiting for buss time-outs. A solution to this difficulty lay in running the acquisition process and the user interface in separate threads, which communicate via simple semaphores and a shared memory scheme. The acquisition process is thus able to run flat out, updating indicators as necessary, while a thread waits for user input. This scheme of separate acquisition and user interface threads was so successful that it has been used in all subsequent data acquisition programs.


42

CHAPTER 5: Test Software

5.5

Water Vap our Radiometer Co de

The water vapour radiometer data gathering program is a good example of the way small, simple code can grow in scope and size to incredible proportions. The program was originally written as a means of gathering data from the water vapour radiometer, via a National Instruments DAQ card, and dumping the data to disk, to facilitate stability tests in the lab. It was never intended to be used in the final acquisition system, but has run in various guises and on various hardware consistently ever since. One memorable test run involved cable-tying laptop PCs running windows to the frame for the L-band feed in the antenna vertex rooms, with a huge tangle of wires coming out of the PCMCIA slot on the PCs, and an ethernet switch similarly cable-tied nearby. Much was learnt in this test (over several months) about the deleterious effect of Ethernet hardware on L-band observations.

5.5.1

Server

The WVR server is the core of the program. It performs periodic reads of all analog channels in the water vapour radiometer, accurately time tags them, and stores them on a local disk file in .csv format, an ASCII format that is simple to import into an Excel spreadsheet. The general format is shown below: Water Vapour Radiometer Logfile 15:05:33, 741.330000, 0.049686, ... -0.000944, -0.006514, 15:05:33, 741.430000, 0.049543, ... -0.000997, -0.006151, 15:05:33, 741.530000, 0.049562, ... -0.001054, -0.006247, The first entry for each line gives the time for the sample in HH:MM:SS format. Next is the time from program start, in seconds, represented as a floating point number. This entry is accurate to within about 1 millisecond, dependant on the PC system clock, which may be locked up to an external reference using the ntp protocol. Subsequent entries are the voltage (in volts) for each of the sampled inputs. It is perfectly possible to run instances of the server entirely stand-alone, without an ethernet link or client. Most of the work involved in writing the server software was in ensuring that it would reliably take data under a wide range of conditions, including disk congestion (due perhaps to network access of previous or current data files), and dealing with the vagaries of running under Windows, where processes can be inexplicably suspended for hundreds of milliseconds for no good reason. The server makes use of a dynamically allocated linked list queue, in order to buffer data, as shown below: typedef struct List { double data[16]; char time[9];


CHAPTER 5: Test Software

43

Figure 5.3: A screendump showing the water vapour radiometer server graphical user interface.

double sec; struct List *next; } list; The server is heavily threaded, in that one thread acquires data and places it in the queue, whilst another thread looks after the user interface. The queue can grow as large as necessary (up to the memory size of the computer). Every ten samples, the acquisition thread tries to open the data file and write out twenty samples (or else the contents of the buffer). In this way, the data file is left closed most of the time so other programs can access it while it is being written. The acquisition program will simply attempt to access the file each ten samples, with its FIFO buffer growing each time, until the file becomes available. At this point, the program writes out twenty records each ten samples, so the FIFO length drops back to zero fairly quickly without a sudden long data transfer disrupting the acquisition process. In addition, a separate thread monitors the TCP/IP connection, and the user interface, and allows a user to start and stop the aquisition, change the sample interval, number of samples per record, etc.

5.5.2

Client

The water vapour radiometer client software acts as a simple remote control for the server. It includes all controls and displays present on the server panel, with the exception of the running chart recorder display, and allows all aspects of data acquisition to be controlled remotely from the central control room. In order to minimise reliance on network connections, the actual data is dumped to a disk locally on the server machine, and not transferred to the client. Each file is


44

CHAPTER 5: Test Software

Figure 5.4: A screendump showing the water vapour radiometer client "remote control" panel.

limited to a number of samples, after which time the server closes the file and creates a new one, with a name based upon the current date and time. In this way, it is possible to transfer data from the server machine to the central site using normal operating system file transfer procedures, transparently to the acquisition process. TCP packets to control the server acquisition are of the following form: struct msg_type { char msgHD; unsigned char msglen; char msg[512]; }; The header is a token to identify a command string. In this case it is simply '71' stored as a character. Next the message length is stored, and finally the actual data, as an ASCII string. Control messages are of the form: COMMAND DATA For example, the following command sets the sample interval to 100msec: INTERVAL 0.10 The server replies to requests with a similarly framed packet, echoing the request message and appending either or depending on whether it was able to to complete the request. For error conditions, it also attempts to provide some information as to what is wrong. In addition, the server periodically updates the client as to the state of acquisition, echoing the number of samples taken and the file to which they have been written every hundred samples, providing some reassurance that the process is working.


CHAPTER 5: Test Software

45

5.6

Summary

A number of different programs have been written to debug and prove operation of different parts of the interfacing system. These programs were written in Labwindows/CVI, mainly due to familiarity with the language and the convenience of being able to run the diagnostics from a Windows notebook. In the case of the water vapour radiometer, the test software served as the main acquisition system for a period of time, reliably gathering data from the radiometers. With the exception of the basic dataset test panel, all other monitor programs make use of a threaded architecture to separate the acquisition and user interface portions of the program, ensuring that neither interferes adversely with the other.


46

CHAPTER 5: Test Software


Chapter 6 Systems Integration and Pro ject Management
Planning is an unnatural process; it is much more fun to do something. The nicest thing about not planning is that failure comes as a complete surprise, rather than being preceded by a period of worry and depression. Sir John Harvey-Jones

6.1

Overview

All these boards, modules, and software don't exist in a vacuum. They must be connected to one another in a robust, maintainable way, and integrated into the antennas. Much of the top level design of this interfacing pro ject was dictated by external factors, such as availability of the telescopes for engineering work, the presence of existing multimode fibres in the telescopes, etc. This has proven to be the most difficult and time consuming part of the pro ject, as it often involves difficult modifications to the telescopes, which must be done in a manner which does not affect observations.

6.2

Fibre Cabling

The millimetre receiver makes use of optical fibre cables already installed through the telescope structure, running from the pedestal room, at the base of the antenna, up through the azimuth and elevation cable wraps to the vertex room, where they terminate in the side of the sampler rack. In order to make use of these fibres, they must be extended to the upper floor of the vertex room, and connected to the millimetre receiver package. To minimise duplication of effort, these fibres are run in the same duct work as single mode fibres carrying the local oscillator signal to and from the receiver. The following tasks were necessary to make use of the current fibres: 47


48

CHAPTER 6: Systems Integration and Pro ject Management · Splicing new connectors on to the ends of the existing fibres, which are compatible with the connectors used on the millimetre receiver. · Installation of "Adaptaflex" flexible conduit between the sampler rack and top floor distribution panel. · Design and installation of a box for the top floor, in which to break out the fibres for the millimetre receiver interface, millimetre receiver Local Oscillator, and C/X interface.

Splicing of fibres and installation of conduit was performed mainly by technicians on-site at Narrabri.

6.2.1

Fibre Mux

The fibre mux is a simple board that allows several fibres, plus a twisted pair buss, to communicate with the ACC via a single fibre pair. This board allows the one fibre connection to control all three receivers (via fibre) plus the existing vertex room twisted pair dataset buss. This saves considerable expense by reducing the number of fibres, plus reducing the number of connections.

Figure 6.1: The fibre mux board. This board allows the use of three fibre connected devices, as well as a twisted pair RS-485 dataset buss on the one ACC fibre.

The design of this board was not especially difficult. All the board does is distribute and buffer the transmitted data from the ACC to all ports, and drive the receive data line back to the ACC with the logical OR of all inputs. In this way, requests from the ACC are transmitted to all datasets, and any reply is relayed back to the ACC. No attempt is made to prevent congestion, as the datasets should only reply when they are addressed.


CHAPTER 6: Systems Integration and Pro ject Management

49

6.2.2

Fibre Mo dems

The original proposal called for the development of a plug in fibre modem to occupy the ACC I/O chassis. Due to time constraints, this subpro ject has been delayed until after the millimetre receiver interfaces are otherwise commissioned. In the meantime, the pro ject makes use of Optical System Devices OSD-135 fibre modems, which serve well with the use of an adapter on both fibres, to the E-2000 standard used by the rest of the pro ject.

6.3

Pro ject Management Issues

This has been a long and at times difficult pro ject. Challenges were overcome in many technical issues, such as how to achieve the required SNR in the water vapour radiometer interface, and also in tackling a large, complex pro ject, involving many facets such as coordination of people, equipment, and time. In order to make some sense of the pro ject, the first step in the design process was to divide the pro ject up into a number of "modules", which could be more easily handled in isolation, rather than one large conglomerate mess. The specifications of each module were defined early on, along with the way the modules connected together. Development of individual modules was done in a traditional waterfall method, whereby the specifications were thrashed out, then a then a prototype designed, constructed and debugged, and finally production units built for use on the array. Perhaps the most difficult aspect of planning a pro ject such as this is that when timescales are originally estimated, one has a tendency to treat the pro ject at hand as though it is the only thing being done. In reality, other tasks and pro jects intrude, causing timescales to stretch beyond those originally predicted. Another issue is that when working with a large instrument such as the Compact Array, one is not able to simply turn up to the telescope with some equipment and install it. Instead, development efforts must mesh with regular maintenance periods and installation shutdowns. Of course, these are the periods where staff availability at the telescopes is at its lowest, with everyone busy dealing with the deluge of problems that must be solved in the limited maintenance time. The timelines developed in the proposal were adhered to in a general sense, if not in detail. The main divergence from the proposal was that the conversion interface front panel has been deferred to a later date, while the conversion interface itself was effectively split in two, with local oscillator control functions separated. This allowed the pro ject to be completed within the allowable time, which was a hard limit in any case due to compact array scheduling.

6.4

Summary

Significant additional work, beyond the design and construction of circuit boards and the writing of software, are necessary before this equipment can be used in real life


50

CHAPTER 6: Systems Integration and Pro ject Management

on the Compact Array antennas. Much of this work is uninteresting and fiddly, and takes an inordinate amount of time to complete, especially when faced with significant obstacles in the allocation of resources to the task, and the synchronisation of work with other users of the facility. The general development process followed in this pro ject is one of top down design in the first instance, and then a simple waterfall process for sub-pro jects identified in the initial pro ject outline. This process is a useful one for this type of equipment, in that it neatly divides up work early in the process, and limits risk to other sub-pro jects should difficulties be encountered with a design. The disadvantage with such a model is that the overall parameters of the design are effectively "cast in stone", and it is difficult to make large changes to the overall system.


Chapter 7 Conclusions and Future Work
What we call the beginning is often the end. And to make an end is to make a beginning. The end is where we start from. T.S. Eliot

7.1

Conclusions

It is no easy task to summarise work done over such a period of time, encompassing so many different disciplines. This is the first time I've been responsible for a pro ject of this breadth and depth, and it has been a very valuable learning exercise. Many of the techniques used in this pro ject are new to my workplace, most especially the use of VHDL to design logic circuitry. Processes established for this pro ject for the use of VHDL in designs have since been used in the development of other equipment. Further, much of the equipment designed as part of this pro ject have found uses in other applications. Most notably, the F83 interface has become a ubiquitous feature of new receiver designs, and has been used in other organisations besides the ATNF. This pro ject started life as a "what if" session late one night whilst commissioning interface equipment for the Parkes radiotelescope, and has since at times appeared almost to have a life of its own. Through applying pro ject management principles, such as doing a work breakdown and timeline for the pro ject fairly early on, much of the unpredictability of the pro ject was tied down. Much was also learnt about the pitfalls associated with pro ject management, such as the tendency for people to ignore external influences when estimating time for completion of a given task. On the whole, this has been a wonderful learning experience. Being able to start with an idea and see it through to fruition as a significant pro ject has been an exciting thing to do.

7.2

Future Work

As intimated in the introduction to this thesis, this pro ject is part of ongoing work. As such, this may be seen as a "slice" of a much longer, larger pro ject. 51


52

CHAPTER 7: Conclusions and Future Work

It is perhaps useful to bring out our crystal ball, and look into the future to see where the interfacing work within the ATNF will take us. The incorporation of the dataset engine within existing electronics has led us in a direction that shows great promise for future equipment. As with many fields, much of the cost of equipment for the ATNF is taken up with interconnections. Using the original datasets necessitated running a huge number of connections across the backplane of a receiver or conversion system to control equipment. The provision of a simple, small, cheap dataset that can be hidden inside modules allows us to reduce the amount of digital and analog wiring to a bare minimum, with concomitant gains in system cost and reduction of noise pickup. The close integration of this relatively high speed digital circuitry with sensitive analog and RF equipment means that a number of challenges must be met, most especially with reducing the RFI emanations from digital equipment, or with mitigating their effects. One possible method of reducing the effect of RFI on analog and RF circuitry may be found in the use of spread spectrum clocks. The asynchronous serial comms used by the dataset is tolerant of significant mismatches between transmitter and receiver clocks. This allows us to dither the respective clocks, such that the energy in clock harmonics is spread over a wide frequency range, and is thus less of an issue. Finally, whilst this pro ject marks the end of my Bachelor of Engineering studies, it also marks the first significant pro ject in my career. I hope to go on to further studies, and undertake many more pro jects as my career unfolds.


Bibliography
Abbott, D., and Hall, P., "A Stable Millimetre-Wave Water Vapour Radiometer", Dec 1999, Journal of Electrical and Electronics Engineering, Australia. Vol. 19, no. 4, pp. 213-225. AMiBA Array for Microwave Background Anisotropy - Pro ject Homepage, Academia Sinica Institute of Astronomy and Astrophysics, 2002 http://www.asiaa.sinica.edu.tw/amiba/ In System Programming Circuits for AT17 EEPROMS with Atmel and Xilinx FPGAs, http://www.atmel.com/atmel/acrobat/doc3030.pdf Atmel FPGA Configurator Programming Kit http://www.atmel.com/dyn/resources/prod documents/DOC0642.PDF Manual,

The Australia Telescope Compact Array Users' Guide, CSIRO ATNF, October 1999 http://www.narrabri.atnf.csiro.au/observing/users guide/html/atug.html Christiansen, W. & HЁ om, J. "Radiotelescopes", 1969, Cambridge University Press, Camogb bridge. p233. DIST Press Release. 1995, "Visionary Science Pro jects Keep Australia at the Leading Edge", http://www.dist.gov.au/events/innovate/r1.html Ferris, R. "Introducing the AT Data-sets", 1991, Australia Telescope National Facility Internal Report. Ferris, R. "AT Data Set Application Software Guide", 1997, Australia Telescope National Facility Internal Report. Graves, G., Bowen, M., Jackson, S., and Sincliar, M., "The Conversion System for the Australia Telescope Millimetre-Wave Receiver System", 2002, Poster paper, Workshop on the Applications of Radio Science, Katoomba. Hall, P., Kesteven, R., Beresford, R., Ferris, R. and Loone, D. "Monitoring and Protection Strategies for the Compact Array", 1992, Journal of Electrical and Electronics Engineering, Australia. IE Aust & IREE Aust. Vol 12, No. 2, pp 211-218. Kernighan, B. and Ritchie, D. "The C Programming Language (2nd Ed.)", 1988, Prentice Hall, New Jersey. Linear Technologies LTC1605-2CG http://www.linear.com/pdf/160512.pdf 16 Bit ADC Data Sheet,

Moorey, G., Gough, R., Graves, G., Leach, M., Sinclair, M., Bolton, R., Bowen, M., Kanoniuk, H., Reilly, L. and Jackson, S. "The Australia Telescope Millimetre Wave Receiver System", 2002, Proc. Workshop on the Applications of Radio Science.

53


54

Bibliography

"Labwindows/CVI Standard Libraries Reference Manual", 1996, National Instruments Corporation, Austin. "Getting Started With Labwindows/CVI", 1996, National Instruments Corporation, Austin. Reilly, L. "F33 Dataset Interface #1 Card", 1997, Australia Telescope National Facility Internal Report. Sinclair, M., Graves, G., Gough, R., Moorey, G. "The Receiver System", 1992, Journal of Electrical and Electronics Engineering, Australia. IE Aust & IREE Aust. Vol 12, No. 2, pp 147-160. Smith, D. "HDL chip design : a practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog", 1996, Doone Publications, Madison. Stevens, R. "TCP/IP Illustrated Volume 1: The Protocols", 1994, Addison-Wesley Publishing Co., Massachusetts. Synopsis Inc. "VeriBest FPGA Synthesis VHDL Reference Manual", 1996, Synopsis. Texas Instruments ADS1252 Data Sheet, http://www-s.ti.com/sc/ds/ads1252.pdf White, D., and Mardiguian, M. "EMI Control, Methodology and Procedures", 1985, Interference Control Technologies, Illinois. Wright, G., and Stevens, R. "TCP/IP Illustrated Volume 2: The Implementation", 1995, Addison-Wesley Publishing Co., Massachusetts. Xilinx Inc. "Xilinx XACT Development System Libraries Guide", 1993, Xilinx. Xilinx Inc. "The Programmable Gate Array Data Book", 2002, Xilinx. Yalamanchili, S. "VHDL Starters Guide", 1998, Prentice Hall, New Jersey.


App endix A AT Dataset Engine VHDL Source
Include the source for the Dataset Engine.

A.1

UART Source

-- MNRF Interface VHDL Code -- Asynchronous receiver/transmitter design ----Revision: 1.3 Commenced: 23/8/99. Last Modified: 5/6/01. Author: Suzy Jackson sjackson@atnf.csiro.au

-- This package contains the bare bones hardware for an asynchronous -- serial receiver (rx), and an asynchronous serial transmitter (tx) -- which will hopefully be of some use to the MNRF generic interface. -- A few notes about the design: ------------The current datasets use 38,400 bits per second (or 4800), 1 start bit, 8 data bits, odd parity, and 1 stop bit. I see no dramatic need to rock the boat here, so lets start with something that does the same... Also it might be nice to allow for higher data rates. With this in mind, the design should be OK for many standard baudrates from 38400bps to 460.8Kbps using the same 3.6864MHz clock. Should baudrates outside this range be desired, the crystal frequency can be changed, or alternatively an external frequency divider could be used to drive the clk input. The Xilinx software gives a maximum clock rate of 25MHz for a "typical" design, utilising a Spartan XCS40XL240-4, so with this chip the baudrate may be pushed up to aroud 2.5Mbps.

-- Receiver Design: -- At present, I've defined the clock to be 3.6864MHz. This divides -- by 96 to give 38400Hz. We really need 8 clocks per bit, so I've

55


56

APPENDIX A: AT Dataset Engine VHDL Source

-- built in a nifty little predivide which can divide from 1 to 16, -- giving us the following bitrates (given by bps = -- fosc/(8*(prescale+1))) ---------------Prescale: 0000 0001 0010 0011 0101 0111 1011 1111 1.2288MHz: 153.6Kbps 76.8Kbps 51.2Kbps 38.4Kbps 25.6Kbps 19.2Kbps 12.8Kbps 9.6Kbps 1.8432MHz: 230.4Kbps 115.2Kbps 76.8Kbps 57.6Kbps 38.4Kbps 28.8Kbps 19.2Kbps 14.4Kbps 3.6864MHz: 460.8Kbps 230.4Kbps 153.6Kbps 115.2Kbps 76.8Kbps 57.6Kbps 38.4Kbps 28.8Kbps 4.9152MHz: 614.4Kbps 307.2Kbps 204.8Kbps 153.6Kbps 102.4Kbps 76.8Kbps 51.2Kbps 38.4Kbps

This means that we really want to sample the data 4 prescaled clocks after a start detection, and then every 8 prescaled clocks to shift in the data, in order to guarantee that we'll be within the bit even if the transmit and receive clocks vary. If we sample in exactly the middle of the first bit, then we can be out by +/-5% (ie lots) before we get framing problems.

-- A start condition is defined by 0 on RXD for three divided clocks. ----The p_err output is logic 1 for an error with odd parity. Obviously, it'll be logic 0 for an error with even parity. f_err is the inverse of the stop bit, so it'll often :) be 1 if there's a framing error.

-- The parity logic is done bit by bit in a serial fashion, rather -- than all at once. Thanks to my ADS class for coming up with this -- neat trick to reduce the gate count. -- parity and framing error outputs are held until the reset is -- pulled (rev 1.2) -- Once we have a byte, we pull full high. Asserting clr will clear -- this and arm us for the next byte. Obviously, the values in -- out_data, p_err, and f_err are only guaranteed when full is high. -- Transmitter Design: ----The transmitter shifting out 0, bits are shifted this is the same takes the form of a simple 10 bit shift register, data(0), data(1)...data(7), odd parity, 1. The out on every 8th clock, so the clock rate for as that for the receiver.

-- Random transmitter parity fixed (rev 1.3) by clearing the ptemp -- bit at the start of each byte, rather than only when reset. --***************************************************************** -Receiver Entity/Architecture Definition


APPENDIX A: AT Dataset Engine VHDL Source
--***************************************************************** library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity rx is port ( rst, clr, clk, rxd: in std_logic; prescale: in std_logic_vector (3 downto 0); byte: out std_logic_vector(7 downto 0); p_err, f_err, full: out std_logic); end rx; architecture archrx of rx is signal signal signal signal signal cnt_reg: unsigned (6 downto 0); pre_cnt: unsigned (3 downto 0); check: std_logic_vector (3 downto 0); temp: std_logic_vector (7 downto 0); ptemp: std_logic;

57

begin byte <= temp; process (clk, rst) begin if rst = '1' then -- reset condition full <= '0'; cnt_reg <= "0000000"; temp <= x"00"; f_err <= '0'; p_err <= '0'; ptemp <= '0'; pre_cnt <= "0000"; elsif clk'event and clk = '1' then if clr = '1' then -- reset for next byte full <= '0'; cnt_reg <= "0000000"; temp <= x"00"; f_err <= '0'; p_err <= '0'; ptemp <= '0'; pre_cnt <= "0000"; check <= rxd & rxd & rxd & rxd; elsif pre_cnt = 0 then if cnt_reg = 0 then -- waiting for start condition - shift data thru start -- detect register check(3 downto 0) <= check(2 downto 0) & rxd; if check = "1000" then


58

APPENDIX A: AT Dataset Engine VHDL Source

-- input 0 for three successive clocks indicates valid -- start. cnt_reg <= "0000001"; else cnt_reg <= "0000000"; end if; elsif cnt_reg = 73 then -- check parity bit ptemp <= ptemp xor (not rxd); cnt_reg <= cnt_reg + 1; elsif cnt_reg = 81 then -- stop bit - assert full and check framing condition full <= '1'; f_err <= not rxd; p_err <= ptemp; check <= "1111"; cnt_reg <= cnt_reg + 1; elsif std_logic_vector(cnt_reg(2 downto 0)) = "001" then -- shift in bit temp(7 downto 0) <= rxd & temp(7 downto 1); ptemp <= ptemp xor rxd; cnt_reg <= cnt_reg + 1; else cnt_reg <= cnt_reg + 1; end if; end if; if pre_cnt = unsigned(prescale) then pre_cnt <= "0000"; else pre_cnt <= pre_cnt + 1; end if; end if; end process; end archrx;

--***************************************************************** -Transmitter Entity/Architecture Definition --***************************************************************** library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity tx is port ( rst, go, clk: in std_logic; prescale: in std_logic_vector(3 downto 0); byte: in std_logic_vector(7 downto 0); txd, empty: out std_logic); end tx;


APPENDIX A: AT Dataset Engine VHDL Source

59

architecture archtx of tx is signal signal signal signal cnt_reg: unsigned (3 downto 0); pre_cnt: unsigned (6 downto 0); temp: std_logic_vector (7 downto 0); ptemp: std_logic;

begin process (rst, clk) begin if rst = '1' then -- reset condition temp <= x"00"; cnt_reg <= "0000"; pre_cnt <= "0000000"; txd <= '1'; empty <= '1'; ptemp <= '0'; elsif clk'event and clk = '1' then if pre_cnt = 0 then if cnt_reg = 0 then -- stop bit - assert empty, feed out stop bit, and stop empty <= '1'; txd <= '1'; if go = '1' then cnt_reg <= "0001"; else cnt_reg <= "0000"; end if; elsif cnt_reg = 1 then -- wait for go pulse to be deasserted; empty <= '0'; if go = '1' then cnt_reg <= "0001"; else cnt_reg <= "0010"; end if; elsif cnt_reg = 2 then -- shift out start bit & initialise temp & ptemp txd <= '0'; empty <= '0'; temp <= byte; cnt_reg <= "0011"; ptemp <= '0'; elsif cnt_reg = 11 then -- shift out parity bit txd <= not ptemp; empty <= '0'; cnt_reg <= "0000"; else txd <= temp(0); ptemp <= ptemp xor temp(0); empty <= '0'; temp(7 downto 0) <= '0' & temp(7 downto 1); cnt_reg <= cnt_reg + 1;


60

APPENDIX A: AT Dataset Engine VHDL Source

end if; end if; if pre_cnt = unsigned(prescale & "111") then pre_cnt <= "0000000"; else pre_cnt <= pre_cnt + 1; end if; end if; end process; end archtx;

A.2

Dataset Source

-- MNRF Interface VHDL Code -- Dataset RS485 Interface Section ----Revision: 1.2 Commenced: 23/8/99. Last Modified: 23/12/900 Author: Suzy Jackson sjackson@atnf.csiro.au uart.vhd

-- Requires:

-- This package contains logic to implement a really raw Dataset, -- including receiver FIFO, address detection, some error detection, -- etc. -- Inputs: -----rst: clk: rxd: baud(3 dsa(4 active high reset. 3.6864MHz clock (or 1.8432MHz with baudrates/2) asynchronous receive line (to interface, from ACC). downto 0): divider for baudrate - bps = 460800/(prescale+1) downto 0): dataset address (should be hardwired to a number)

-- Bidirectional: -- data(15 downto 0): -- Outputs: --------address(8 downto 0): address being read (or written). wr: active high read*/write line. stb: data strobe txd: asynchronous transmit byte (from interface) txd_en: active high transmit enable (used for lighting up RS485 transmitter) par: active high parity error signal. err: active high framing error signal. Data bus - tristate - gated by the wr output.


APPENDIX A: AT Dataset Engine VHDL Source

61

-----

The length and validity of these signals is entirely dependent on the comms (serial) speed. At a minimum (using a 38.4bps link at maximum rate with a 3.6864MHz crystal) we have the following diagrams:

-- Monitor Read: --Address: --Wr: --Stb: --Data: -----T1-T2 T2-T3 T2-T4 T4-T5 min max min min = = = =

___________________ XXXX___________________XXXX XXXX___________________XXXX ________ _________| |________ ______ XXXX----XXXXX______>---XXXX 1 2 3 45 6

286 us (address setup time) 286 us (read time - stb to data valid) 572 us (minimum strobe length - data must remain valid) 0 (minimum data hold time)

-- Control Write: --Address: --Wr: --Stb: --Data: -----T1-T2 T2-T3 T3-T4 T4-T5 min min min min = = = =

___________________ XXXX___________________XXXX ___________________ XXXX XXXX ________ _________| |________ ______________ XXXXXXXXX______________XXXX 1 23 (address (minimum (minimum (minimum 4 5

286 270 572 286

us ns us us

setup time) time between data valid and strobe edge) strobe length - data valid) data hold time)

-- rev 1.1: --- rev 1.2: -------

Added err (framing error) and par (parity error) outputs, so that we can monitor such things with LEDs. Changed the timing of the address strobe (STB) output, to guarantee that data is valid before its leading edge, as some equipment (F35 and F61) erroneously latch data on the leading edge of the address strobe. Also removed the HBE signal, as it was not really correct. A separate state machine is now used to adapt the 16 bit dataset engine to an 8 bit buss.

--*****************************************************************


62

APPENDIX A: AT Dataset Engine VHDL Source

-Dataset Entity/Architecture Definition --***************************************************************** library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; -- uncomment this line if synthesising use ieee.numeric_std.all; -- uncomment this line if simulating entity dataset is port ( rst, clk, rxd: in std_logic; baud: in std_logic_vector(3 downto 0); dsa: in std_logic_vector(4 downto 0); data: inout std_logic_vector(15 downto 0); add: out std_logic_vector(8 downto 0); stb, wr, txd, txd_en, par, err: out std_logic); end dataset; architecture archdataset of dataset is component rx port( rst, clr, clk, rxd: in std_logic; prescale: in std_logic_vector(3 downto 0); byte: out std_logic_vector(7 downto 0); p_err, f_err, full: out std_logic); end component; component tx port( rst, go, clk: in std_logic; prescale: in std_logic_vector(3 downto 0); byte: in std_logic_vector(7 downto 0); txd, empty: out std_logic); end component; constant constant constant constant constant constant constant constant constant constant ACK: BEL: NAK: SYN: ESC: ASC0: ASC1: ASC2: ASC3: ASC4: std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 std_logic_vector(7 downto downto downto downto downto downto downto downto downto downto 0):= 0):= 0):= 0):= 0):= 0):= 0):= 0):= 0):= 0):= "00000110"; "00000111"; "00010101"; "00010110"; "00011011"; "00110000"; "00110001"; "00110010"; "00110011"; "00110100";

type rxstate_type is (idle, recv_dsa, recv_fn, recv_fn2, recv_high, recv_high2, recv_low, recv_low2); type txreq_type is (idle, send_ack, send_nak); type txstate_type is (unload, idle, send_err, send_warn, send_ack, send_high, send_high2, send_low, send_low2, send_nak, cmd_err, cmd_warn); signal rxbyte, txbyte, error: std_logic_vector(7 downto 0);


APPENDIX A: AT Dataset Engine VHDL Source
signal signal signal signal signal signal --rxstate: rxstate_type; txreq: txreq_type; txstate: txstate_type; rxfull, p_err, f_err, txgo, rxgo, cmd, txempty: std_logic; bufdata: std_logic_vector(9 downto 0); dataout: std_logic_vector(15 downto 0);

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for SER_RX: rx use entity work.rx; for SER_TX: tx use entity work.tx;

begin SER_RX: rx port map (rst, rxgo, clk, rxd, baud, rxbyte, p_err, f_err, rxfull); SER_TX: tx port map (rst, txgo, clk, baud, txbyte, txd, txempty); data <= dataout when (cmd = '1') else "ZZZZZZZZZZZZZZZZ"; stb <= '1' when (txstate = send_ack) or (txstate = send_low) or (txstate = send_low2) or (txstate = send_high) or (txstate = send_high2) or (txstate = cmd_err) or (txstate = cmd_warn) else '0'; wr <= cmd; txd_en <= '0' when (txstate = idle) else '1'; rxgo <= rxfull; par <= p_err; err <= f_err; receive: process (clk, rst) begin if rst = '1' then -- asynchronous reset condition rxstate <= idle; txstate <= idle; txreq <= idle; txgo <= '0'; dataout <= x"0000"; add <= "000000000"; txbyte <= x"00"; error <= x"00"; cmd <= '0'; elsif clk'event and clk = '1' then case rxstate is when idle => -- Wait for SYN character if rxfull = '1' then if (rxbyte = SYN and p_err = '0' and f_err = '0') then -- SYN character - next byte should be dataset address rxstate <= recv_dsa; else rxstate <= idle;


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end if; else rxstate <= idle; end if;

APPENDIX A: AT Dataset Engine VHDL Source

when recv_dsa => -- Get Dataset Address byte -- note that we can't get an escape in this byte. if rxfull = '1' then if (rxbyte(5 downto 1) = dsa(4 downto 0) and p_err = '0' and f_err = '0') then -- yay! We're being addressed rxstate <= recv_fn; add(8) <= rxbyte(0); cmd <= rxbyte(7); elsif (rxbyte = SYN and p_err = '0' and f_err = '0') then -- SYN character - abort. Next byte should be dataset add rxstate <= recv_dsa; else -- not for us - wait for the next packet rxstate <= idle; end if; else rxstate <= recv_dsa; end if; when recv_fn => -- Get Function Address byte if rxfull = '1' then if (p_err = '1' or f_err = '1') then -- malformed byte - send back a NAK. error (1) <= '1'; txreq <= send_nak; rxstate <= idle; elsif rxbyte = ESC then -- escape character - function address in next byte rxstate <= recv_fn2; elsif rxbyte = SYN then -- SYN character - abort. Next byte should be dataset add error (2) <= '1'; txreq <= send_nak; rxstate <= recv_dsa; else -- rxbyte contains function address add(7 downto 0) <= rxbyte(7 downto 0); rxstate <= recv_high; end if; else rxstate <= recv_fn; end if; when recv_fn2 => -- Get Function Address byte after ESC if rxfull = '1' then if (p_err = '1' or f_err = '1') then


APPENDIX A: AT Dataset Engine VHDL Source
-- malformed byte - send back a NAK. error (1) <= '1'; txreq <= send_nak; rxstate <= idle; elsif rxbyte = ASC0 then -- ascii 0 - byte is esc add(7 downto 0) <= ESC; rxstate <= recv_high; elsif rxbyte = ASC1 then -- ascii 1 - byte is syn add(7 downto 0) <= SYN; rxstate <= recv_high; elsif rxbyte = SYN then -- SYN character - abort. Next byte should be dataset add error (2) <= '1'; txreq <= send_nak; rxstate <= recv_dsa; else -- byte is broken - send back a NAK error (3) <= '1'; txreq <= send_nak; rxstate <= idle; end if; else rxstate <= recv_fn2; end if; when recv_high => -- Get High data byte if rxfull = '1' then if (p_err = '1' or f_err = '1') then -- malformed byte - send back a NAK. error (1) <= '1'; txreq <= send_nak; rxstate <= idle; elsif rxbyte = ESC then -- escape character - high_byte in next byte rxstate <= recv_high2; elsif rxbyte = SYN then -- SYN character - abort. Next byte should be dataset add error (2) <= '1'; txreq <= send_nak; rxstate <= recv_dsa; else -- byte contains high data byte dataout(15 downto 8) <= rxbyte(7 downto 0); rxstate <= recv_low; end if; else rxstate <= recv_high; end if; when recv_high2 => -- Get High data byte after ESC

65


66

APPENDIX A: AT Dataset Engine VHDL Source
if rxfull = '1' then if (p_err = '1' or f_err = '1') then -- malformed byte - send back a NAK. error (1) <= '1'; txreq <= send_nak; rxstate <= idle; elsif rxbyte = ASC0 then -- ascii 0 - byte is ESC dataout(15 downto 8) <= ESC; rxstate <= recv_low; elsif rxbyte = ASC1 then -- ascii 1 - byte is SYN dataout(15 downto 8) <= SYN; rxstate <= recv_low; elsif rxbyte = SYN then -- SYN character - abort. Next byte should be dataset add error (2) <= '1'; txreq <= send_nak; rxstate <= recv_dsa; else -- byte is broken - send back a NAK error (3) <= '1'; txreq <= send_nak; rxstate <= idle; end if; else rxstate <= recv_high2; end if; when recv_low => -- Get Low data byte if rxfull = '1' then if (p_err = '1' or f_err = '1') then -- malformed byte - send back a NAK. error (1) <= '1'; txreq <= send_nak; rxstate <= idle; elsif rxbyte = ESC then -- ESC character - low_byte in next byte rxstate <= recv_low2; elsif rxbyte = SYN then -- SYN character - abort. Next byte should be dataset add error (2) <= '1'; txreq <= send_nak; rxstate <= recv_dsa; else -- byte contains low data byte dataout(7 downto 0) <= rxbyte(7 downto 0); txreq <= send_ack; rxstate <= idle; end if; else rxstate <= recv_low;


APPENDIX A: AT Dataset Engine VHDL Source
end if; when recv_low2 => -- Get Low data byte after ESC if rxfull = '1' then if (p_err = '1' or f_err = '1') then -- malformed byte - send back a NAK. error (1) <= '1'; txreq <= send_nak; rxstate <= idle; elsif rxbyte = ASC0 then -- ascii 0 - byte is ESC dataout(7 downto 0) <= ESC; txreq <= send_ack; rxstate <= idle; elsif rxbyte = ASC1 then -- ascii 1 - byte is SYN dataout(7 downto 0) <= SYN; txreq <= send_ack; rxstate <= idle; elsif rxbyte = SYN then -- SYN character - abort. Next byte should be dataset add error (2) <= '1'; txreq <= send_nak; rxstate <= recv_dsa; else -- byte is broken - send back a NAK error (3) <= '1'; txreq <= send_nak; rxstate <= idle; end if; else rxstate <= recv_low2; end if; when others => rxstate <= idle; end case; case txstate is when send_ack => -- Send ACK code if (txempty = '1' and txgo = '0') then txbyte <= ACK; txgo <= '1'; txreq <= idle; if cmd = '1' then -- command - no need to send out byte txstate <= cmd_err; else -- monitor - need to supply byte txstate <= send_high;

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end if; elsif txempty = '0' then txstate <= send_ack; txgo <= '0'; else txstate <= send_ack; txgo <= '1'; end if;

APPENDIX A: AT Dataset Engine VHDL Source

when send_high => -- Send high byte if (txempty = '1' and txgo = '0') then txgo <= '1'; if (data(15 downto 8) = ACK or data(15 downto 8) = NAK or data(15 downto 8) = BEL or data(15 downto 8) = ESC) then -- gotta send out an ESC txbyte <= ESC; txstate <= send_high2; else -- out goes the byte txstate <= send_low; txbyte(7 downto 0) <= data(15 downto 8); end if; elsif txempty = '0' then txstate <= send_high; txgo <= '0'; else txstate <= send_high; txgo <= '1'; end if; when send_high2 => -- Send high byte after ESC if (txempty = '1' and txgo = '0') then txgo <= '1'; if data(15 downto 8) = ESC then -- send out ascii 0 txbyte <= ASC0; elsif data(15 downto 8) = ACK then -- send out ascii 2 txbyte <= ASC2; elsif data(15 downto 8) = BEL then -- send out ascii 3 txbyte <= ASC3; else -- send out ascii 4 txbyte <= ASC4; end if; txstate <= send_low; elsif txempty = '0' then txstate <= send_high2; txgo <= '0'; else txstate <= send_high2;


APPENDIX A: AT Dataset Engine VHDL Source
txgo <= '1'; end if; when send_low => -- Send low byte if (txempty = '1' and txgo = '0') then txgo <= '1'; if (data(7 downto 0) = ACK or data(7 downto 0) = NAK or data(7 downto 0) = BEL or data(7 downto 0) = ESC) then -- gotta send out an ESC txbyte <= ESC; txstate <= send_low2; else -- out goes the byte txstate <= unload; txbyte <= data(7 downto 0); end if; elsif txempty = '0' then txstate <= send_low; txgo <= '0'; else txstate <= send_low; txgo <= '1'; end if; when send_low2 => -- Send low byte after ESC if (txempty = '1' and txgo = '0') then txgo <= '1'; if data(7 downto 0) = ESC then -- send out ascii 0 txbyte <= ASC0; elsif data(7 downto 0) = ACK then -- send out ascii 2 txbyte <= ASC2; elsif data(7 downto 0) = BEL then -- send out ascii 3 txbyte <= ASC3; else -- send out ascii 4 txbyte <= ASC4; end if; txstate <= unload; elsif txempty = '0' then txstate <= send_low2; txgo <= '0'; else txstate <= send_low2; txgo <= '1'; end if; when send_nak => -- Send NAK code if (txempty = '1' and txgo = '0') then txbyte <= NAK;

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txgo <= '1'; txreq <= idle; txstate <= send_err; elsif txempty = '0' then txstate <= send_nak; txgo <= '0'; else txstate <= send_nak; txgo <= '1'; end if;

APPENDIX A: AT Dataset Engine VHDL Source

when send_err => -- Send error codes if (txempty = '1' and txgo = '0') then txbyte <= error; error <= x"00"; txgo <= '1'; txreq <= idle; txstate <= send_warn; elsif txempty = '0' then txstate <= send_err; txgo <= '0'; else txstate <= send_err; txgo <= '1'; end if; when send_warn => -- Send warning codes - not implemented. if (txempty = '1' and txgo = '0') then txbyte <= x"00"; txgo <= '1'; txreq <= idle; txstate <= unload; elsif txempty = '0' then txstate <= send_warn; txgo <= '0'; else txstate <= send_warn; txgo <= '1'; end if; when cmd_err => -- Send error codes for command (no error condition exists) if (txempty = '1' and txgo = '0') then txbyte <= x"00"; txgo <= '1'; txreq <= idle; txstate <= cmd_warn; elsif txempty = '0' then txstate <= cmd_err; txgo <= '0'; else txstate <= cmd_err;


APPENDIX A: AT Dataset Engine VHDL Source
txgo <= '1'; end if; when cmd_warn => -- Send warning codes for command (no error condition exists) if (txempty = '1' and txgo = '0') then txbyte <= x"00"; txgo <= '1'; txreq <= idle; txstate <= unload; elsif txempty = '0' then txstate <= cmd_warn; txgo <= '0'; else txstate <= cmd_warn; txgo <= '1'; end if; when unload => -- make sure we flush the transmit buffer if (txempty = '1' and txgo = '0') then txstate <= idle; elsif txempty = '0' then txgo <= '0'; txstate <= unload; else txstate <= unload; txgo <= '1'; end if; when idle => if txreq = send_ack then txstate <= send_ack; elsif txreq = send_nak then txstate <= send_nak; else txstate <= idle; end if; when others => txstate <= idle; end case; end if; end process; end archdataset;

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A.3

F83 ADC Sequencer Source

-- MNRF Interface VHDL Code


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-- F83 ADC Read Tool -----

APPENDIX A: AT Dataset Engine VHDL Source

Revision: 1.0 Commenced: 21/2/01. Last Modified: 21/2/01 Author: Suzy Jackson sjackson@atnf.csiro.au

-- This package contains the hardware necessary to drive the -- LTC1605-2 ADC as found on the F83 interface board. -- Unlike adcread, which scales and offsets the result to maintain -- some level of compatability with a D2 dataset, this code simply -- presents the ADC data unmolested, in 16 bit signed format. -- Inputs: ----------rst: clk: adcrq: stb: Active high reset signal. Typically the 3.6864MHz system clock, but should be fairly flexible. ADC request input. Should be driven from an address decoder. Address strobe. Connect straight to the relevant dataset module line. This line in conjunction with the ane line enables the data tri-states. 8 bit muxed data input from ADC. Busy output from ADC (active low).

adcdata: busy:

-- Outputs: ----data: 16 bit Tri states containing result of the ADC conversion anst: ADC conversion start pulse. adcen: ADC enable line (active low) anhigh: Select between bytes of ADC result.

--***************************************************************** -ADCRd16 Entity/Architecture Definition --***************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- uncomment this line if synthesising --use ieee.numeric_std.all; -- uncomment this line if simulating entity adcrd16 is port ( rst, clk, adcrq, stb, busy: in std_logic; adcdata: in std_logic_vector (7 downto 0); data: inout std_logic_vector (15 downto 0); anst, adcen, anhigh: out std_logic); end adcrd16; architecture archadc of adcrd16 is


APPENDIX A: AT Dataset Engine VHDL Source
type sttype is signal state: signal result: signal delay: begin data <= result when (adcrq = '1' and stb = '1') else "ZZZZZZZZZZZZZZZZ"; with state select anst <= '0' when start, '1' when others; with adcrq select adcen <= '1' when '0', '0' when others; with state select anhigh <= '1' when high, '0' when others; process (clk, rst) begin if rst = '1' then -- reset condition state <= idle; result <= x"0000"; elsif clk'event and clk = '1' then case state is when idle => -- wait for next valid strobe delay <= "000000"; if (adcrq = '1' and stb = '1') then state <= acq; else state <= idle; end if; when acq => -- Acquire delay - 64 clocks (8.7us at 7.3728MHz) delay <= delay + 1; if delay = 63 then state <= start; else state <= acq; end if; when start => -- ADC read - start conversion state <= check; when check => -- ADC read - wait for busy to fall. if (busy = '0') then state <= check; else state <= high; end if; when high => -- ADC read - latch high byte result (15 downto 8) <= adcdata; state <= low; when low => -- ADC read - latch low byte result (7 downto 0) <= adcdata; state <= finished; when finished => -- All done - waiting for stb to fall; (start, high, low, check, idle, finished, acq); sttype; std_logic_vector (15 downto 0); unsigned (5 downto 0);

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APPENDIX A: AT Dataset Engine VHDL Source
if stb = '1' then state <= finished; else state <= idle; end if; when others => state <= idle;

end case; end if; end process; end archadc;

A.4

F83 Bus Controller Source

-- MNRF Interface VHDL Code -- Dataset 8 bit buss adapter ----Revision: 1.0 Commenced: 27/2/2001. Last Modified: 27/2/2001 Author: Suzy Jackson sjackson@atnf.csiro.au

-- This package contains a simple sequencer to drive an 8 bit buss from -- the 16 bit buss provided by the dataset block. -- Inputs: -----rst: active high reset. clk: 3.6864MHz clock (nominally) stb16: active high data strobe from dataset block wr: active high read*/write line from dataset block en: active high enable line.

-- Bidirectional: -- Data_16 (15 downto 0): 16 bit data buss from dataset -- Data_8 (7 downto 0): 8 bit data buss -- Outputs: -- stb8: data strobe -- hbe: a line indicating whether the high byte (1) or low byte (0) -is being used. -- Monitor Read: --Wr: XXXX___________________________XXXX -________________ -Stb16: _________| |________ -___________


APPENDIX A: AT Dataset Engine VHDL Source
-------Data16: Hbe: Stb8: Data8: XXXX---------XXXX ___ __________| |____________________ _ _ ___________| |_| |_________________ __ __ XXXX-------<__><__>------------XXXX

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-- Control Write: --Wr: --Stb16: --Data16: --Hbe: --Stb8: --Data8:

___________________________ XXXX ________ _________| |________________ ______________ XXXXXXXXX______________XXXXXXXXXXXX ___ ___________________| |___________ _ _ ____________________| |_| |________ ___ ___ XXXXXXXXXXXXXXXXXXXX___X___XXXXXXXX XXXX

--***************************************************************** -buss8 Entity/Architecture Definition --***************************************************************** library ieee; use ieee.std_logic_1164.all; entity buss8 is port ( rst, clk, stb16, wr, en: in std_logic; data16: inout std_logic_vector(15 downto 0); data8: inout std_logic_vector (7 downto 0); stb8, hbe: out std_logic); end buss8; architecture archbus of buss8 is

type state_type is (idle, rd_a, rd_b, rd_c, rd_d, rd_e, rd_f, wr_a, wr_b, wr_c, wr_d, wr_e, wr_f, wr_g); signal state: state_type; signal data: std_logic_vector (15 downto 0); begin

data16 <= data when (wr = '0') and (stb16 = '1') and (en = '1') else "ZZZZZZZZZZZZZZZZ"; hbe <= '1' when state = rd_a else


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'1' when '1' when '1' when '1' when '1' when '0'; state state state state state = = = = = rd_b rd_c wr_b wr_c wr_d

APPENDIX A: AT Dataset Engine VHDL Source
else else else else else

stb8 <= '1' when '1' when '1' when '1' when '0';

state state state state

= = = =

rd_b rd_e wr_c wr_f

else else else else

data8 <= data (15 downto 8) when state = wr_b else data (15 downto 8) when state = wr_c else data (15 downto 8) when state = wr_d else data (7 downto 0) when state = wr_e else data (7 downto 0) when state = wr_f else data (7 downto 0) when state = wr_g else "ZZZZZZZZ"; process (clk, rst) begin if rst = '1' then -- asynchronous reset condition state <= idle; elsif clk'event and clk = '1' then case state is when idle => -- Waiting for something to happen if (wr = '0') and (stb16 = '1') and (en = '1') then state <= rd_a; elsif (wr = '1') and (stb16 = '1') and (en = '1') then state <= wr_a; else state <= idle; end if; when rd_a => state <= rd_b; when rd_b => data (15 downto 8) <= data8; state <= rd_c; when rd_c => state <= rd_d; when rd_d => state <= rd_e; when rd_e => data (7 downto 0) <= data8; state <= rd_f; when rd_f => if stb16 = '0' then state <= idle; else state <= rd_f; end if;


APPENDIX A: AT Dataset Engine VHDL Source
when wr_a => -- Wait for stb16 to fall again if stb16 = '0' then state <= wr_b; else data <= data16; state <= wr_a; end if; when wr_b => state <= wr_c; when wr_c => state <= wr_d; when wr_d => state <= wr_e; when wr_e => state <= wr_f; when wr_f => state <= wr_g; when wr_g => state <= idle; when others => state <= idle; end case; end if; end process; end archbus;

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A.5

WVR ADC Sequencer Source

-- MNRF Interface VHDL Code -- WVR ADC Read Tool ----Revision: 1.0 Commenced: 10/8/01. Last Modified: 10/8/01 Author: Suzy Jackson sjackson@atnf.csiro.au

-- This package contains the hardware necessary to drive the ADS1252 -- ADC as found on the WVR interface board. -- Inputs: -------rst: clk: add: stb: Active high reset signal. 3.6864MHz system clock. Dataset address lines (3 bits). Address strobe. Connect straight to the relevant dataset module line. This line in conjunction with the ane line enables the data tri-states.


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-- ane: -- adcdata: -- Outputs: ---------data: adcclk: adcsclk: muxadd:

APPENDIX A: AT Dataset Engine VHDL Source
Address enable. Connect to the address decoder. Serial data input from ADC.

24 bit Tri states containing result of the addressed ADC conversion ADC conversion clock. ADC serial clock. Multiplexer address.

The ADC is a little tricky to control, both because its speed is excessively slow, and because there is no simple way to start conversions. The ADC simply runs asynchronously, outputting data when it has finished a conversion.

-- These limitations are dealt with in two ways. First, all eight -- channels are locally buffered. The ADC sequencer simply updates all -- eight registers every 20msec. ----In order to do this, the ADC is run at a 1.6KHz conversion rate. This allows eight conversions per channel, satisfying the ADC digital filter settling requirement of six conversions. All but the eighth conversion are discarded.

-- This results in a clk frequency of 614,400 Hz, or 1/6th of the -- oscillator frequency. -- The mux is updated after each conversion. --***************************************************************** -wvradc24 Entity/Architecture Definition --***************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- uncomment this line if synthesising --use ieee.numeric_std.all; -- uncomment this line if simulating entity wvradc24 is port ( rst, clk, stb, ane, adcdata: in std_logic; add: in std_logic_vector (3 downto 0); data: inout std_logic_vector (23 downto 0); muxadd: out std_logic_vector (2 downto 0); mux1en, mux2en, adcclk, adcsclk: out std_logic); end wvradc24; architecture archadc of wvradc24 is type sttype is (idle, dout, getdata, check, transfer); signal state: sttype; signal result0: std_logic_vector (23 downto 0);


APPENDIX A: AT Dataset Engine VHDL Source
signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal begin data <= result0 when (ane = '1' and stb result1 when (ane = '1' and stb result2 when (ane = '1' and stb result3 when (ane = '1' and stb result4 when (ane = '1' and stb result5 when (ane = '1' and stb result6 when (ane = '1' and stb result7 when (ane = '1' and stb result8 when (ane = '1' and stb result9 when (ane = '1' and stb result10 when (ane = '1' and stb result11 when (ane = '1' and stb result12 when (ane = '1' and stb result13 when (ane = '1' and stb result14 when (ane = '1' and stb result15 when (ane = '1' and stb "ZZZZZZZZZZZZZZZZZZZZZZZZ"; muxadd <= mux1en <= mux2en <= adcsclk <= = = = = = = = = = = = = = = = = '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and '1' and add = "0000") add = "0001") add = "0010") add = "0011") add = "0100") add = "0101") add = "0110") add = "0111") add = "1000") add = "1001") add = "1010") add = "1011") add = "1100") add = "1101") add = "1110") add = "1111") else else else else else else else else else else else else else else else else result1: std_logic_vector (23 downto result2: std_logic_vector (23 downto result3: std_logic_vector (23 downto result4: std_logic_vector (23 downto result5: std_logic_vector (23 downto result6: std_logic_vector (23 downto result7: std_logic_vector (23 downto result8: std_logic_vector (23 downto result9: std_logic_vector (23 downto result10: std_logic_vector (23 downto result11: std_logic_vector (23 downto result12: std_logic_vector (23 downto result13: std_logic_vector (23 downto result14: std_logic_vector (23 downto result15: std_logic_vector (23 downto serclk: std_logic; temp: std_logic_vector (23 downto 0); waitcnt: unsigned (5 downto 0); bit: unsigned (4 downto 0); channel: unsigned (3 downto 0); clkdiv: unsigned (2 downto 0); sixth: unsigned (3 downto 0); 0); 0); 0); 0); 0); 0); 0); 0); 0); 0); 0); 0); 0); 0); 0);

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std_logic_vector (channel (2 downto 0)); not std_logic (channel(3)); std_logic (channel(3)); serclk;

process (clk, rst) begin if rst = '1' then adcclk <= '0'; clkdiv <= "000";


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waitcnt <= "000000"; state <= idle; bit <= "00000"; channel <= "0000"; serclk <= '0'; sixth <= "0000";

APPENDIX A: AT Dataset Engine VHDL Source

elsif clk'event and clk = '1' then -- generate adc clock (614400 Hz) if clkdiv = 2 then adcclk <= '1'; clkdiv <= clkdiv + 1; elsif clkdiv = 5 then clkdiv <= "000"; adcclk <= '0'; else clkdiv <= clkdiv + 1; end if; case state is when idle => -- wait for data line to go low waitcnt <= "000000"; if adcdata = '0' then state <= dout; else state <= idle; end if; when dout => -- wait 64 clocks. if adcdata = '1' then if waitcnt = 63 then state <= getdata; bit <= "00000"; else waitcnt <= waitcnt + 1; state <= dout; end if; else state <= dout; end if; when getdata => -- data available - clock into temp register. if bit = 24 then state <= check; serclk <= '0'; elsif serclk = '0' then temp <= temp (22 downto 0) & not adcdata; bit <= bit + 1; state <= getdata; serclk <= '1'; else serclk <= '0'; state <= getdata; end if; when check => -- we only want the sixth conversion on a given mux address... sixth <= sixth + 1;


APPENDIX A: AT Dataset Engine VHDL Source
if sixth = 15 then state <= transfer; else state <= idle; end if; when transfer => -- transfer temp into relevant result register. sixth <= "0000"; if (ane = '0' or stb = '0') then -- make sure we can't conflict with a read of the register if channel = 0 then result0 <= temp; elsif channel = 1 then result1 <= temp; elsif channel = 2 then result2 <= temp; elsif channel = 3 then result3 <= temp; elsif channel = 4 then result4 <= temp; elsif channel = 5 then result5 <= temp; elsif channel = 6 then result6 <= temp; elsif channel = 7 then result7 <= temp; elsif channel = 8 then result8 <= temp; elsif channel = 9 then result9 <= temp; elsif channel = 10 then result10 <= temp; elsif channel = 11 then result11 <= temp; elsif channel = 12 then result12 <= temp; elsif channel = 13 then result13 <= temp; elsif channel = 14 then result14 <= temp; else result15 <= temp; end if; channel <= channel + 1; state <= idle; else state <= transfer; end if; when others => state <= idle; end case; end if; end process; end archadc;

81


82

APPENDIX A: AT Dataset Engine VHDL Source


App endix B F83 Interface Schematics

1

2

3

4

ADC 1.sch
D

Digital IO 2.sch
D

Connector.sch

Xilinx 1.sch

Digital IO 1.sch

Power Supply.sch

C

C

B

B

Drawn:

Date:

ATNF RECEIVER GROUP F83 Interface Board
A

Checked:

Approved:

A
Originator:

Project Sheet
Schematic Filename:

Issued:

K:\F83 PCB\Main Board.prj
Revision: Sheet: Total:

Assembly Drawing No.:

1.0
1 2 3 4

1

7

Figure B.1: F83 interface pro ject sheet

83


84

1

2

3

4

D

D

C

C

VCC

+5V

U21

ANALOG IN 200R 0.1% D2 BZV55C4V3 C1 4n7 C4 2u2 C2 2u2 33K2 0.1%

R1

R2

C39 10uF

C42 10uF

D3 BZV55C4V3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 VIN AGND1 REF CAP AGND2 D15(MSB) D14 D13 D12 D11 D10 D9 D8 DGND VDIG VANA BUSY CS R/C BYTE D0 D1 D2 D3 D4 D5 D6 D7

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AnBSY AnEN AnST HIGH D0 D1 D2 D3 D4 D5 D6 D7

Figure B.2: F83 interface ADC schematic
LTC1605-2CG
Drawn: Date: Checked: Approved: Originator:

B

B

ATNF RECEIVER GROUP F83 Interface Board
A

A

ADC
Issued: Schematic Filename:

K:\F83 PCB\ADC 1.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

2

7

APPENDIX B: F83 Interface Schematics

1


1

2

3

4

5

6

7

8

U1

U4

D

DIG2/3 DIG2/7 DIG2/2 DIG2/6 DIG2/1 DIG2/5 DIG2/0 DIG2/4
A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 2 3 5 6 8 9 11 12

47 46 44 43 41 40 38 37

BDIG2/3 BDIG2/7 BDIG2/2 BDIG2/6 BDIG2/1 BDIG2/5 BDIG2/0 BDIG2/4 DIG8/3 DIG8/2 DIG8/1 DIG8/0
47 46 44 43 41 40 38 37 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 2 3 5 6 8 9 11 12

BDIG8/3 BDIG8/2 BDIG8/1 BDIG8/0

D

DIG1/3 DIG1/7 DIG1/2 DIG1/6 DIG1/1 DIG1/5 DIG1/0 DIG1/4
A8 A9 A1 A1 A1 A1 A1 A1 0 1 2 3 4 5 0 1 2 3 4 5 B8 B9 B10 B11 B12 B13 B14 B15 13 14 16 17 19 20 22 23 A8 A9 A1 A1 A1 A1 A1 A1 B8 B9 B10 B11 B12 B13 B14 B15

36 35 33 32 30 29 27 26

BDIG1/3 BDIG1/7 BDIG1/2 BDIG1/6 BDIG1/1 BDIG1/5 BDIG1/0 BDIG1/4 DIG7/3 DIG7/7 DIG7/2 DIG7/6 DIG7/1 DIG7/5 DIG7/0 DIG7/4
36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23

BDIG7/3 BDIG7/7 BDIG7/2 BDIG7/6 BDIG7/1 BDIG7/5 BDIG7/0 BDIG7/4 U7 DIG13/3 DIG13/0 DIG13/4 DIG13/1 DIG13/5 DIG13/2
47 46 44 43 41 40 38 37 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 2 3 5 6 8 9 11 12

Dir2 Dir1
VCC

48 25 1 24 OE1 OE2 T/R1 T/R2

Dir8 Dir7
VCC

48 25 1 24 OE1 OE2 T/R1 T/R2

BDIG13/3 BDIG13/0 BDIG13/4 BDIG13/1 BDIG13/5 BDIG13/2

74ACTQ16245 C7 100n DIG14/3 DIG14/0 DIG14/4 DIG14/1 DIG14/5 DIG14/2
36 35 33 32 30 29 27 26 A8 A9 A1 A1 A1 A1 A1 A1 0 1 2 3 4 5 B8 B9 B10 B11 B12 B13 B14 B15 13 14 16 17 19 20 22 23

74ACTQ16245 C8 100n BDIG14/3 BDIG14/0 BDIG14/4 BDIG14/1 BDIG14/5 BDIG14/2

C

U2

U5

C

Dir13 Dir14 74ACTQ16245

48 25 1 24 OE1 OE2 T/R1 T/R2

VCC

APPENDIX B: F83 Interface Schematics

DIG4/1 DIG4/3 DIG4/0 DIG4/2
A8 A9 A1 A1 A1 A1 A1 A1 0 1 2 3 4 5 0 1 2 3 4 5 B8 B9 B10 B11 B12 B13 B14 B15 13 14 16 17 19 20 22 23 A8 A9 A1 A1 A1 A1 A1 A1 B8 B9 B10 B11 B12 B13 B14 B15

47 46 44 43 41 40 38 37 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7

2 3 5 6 8 9 11 12

BDIG4/1 BDIG4/3 BDIG4/0 BDIG4/2 BDIG3/3 BDIG3/7 BDIG3/2 BDIG3/6 BDIG3/1 BDIG3/5 BDIG3/0 BDIG3/4 DIG10/4 DIG10/0 DIG10/5 DIG10/1 DIG10/6 DIG10/2 DIG10/7 DIG10/3
36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23

DIG9/4 DIG9/0 DIG9/5 DIG9/1 DIG9/6 DIG9/2 DIG9/7 DIG9/3
47 46 44 43 41 40 38 37 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 2 3 5 6 8 9 11 12

BDIG9/4 BDIG9/0 BDIG9/5 BDIG9/1 BDIG9/6 BDIG9/2 BDIG9/7 BDIG9/3 BDIG10/4 BDIG10/0 BDIG10/5 BDIG10/1 BDIG10/6 BDIG10/2 BDIG10/7 BDIG10/3 U8
VCC

C13 100n

DIG3/3 DIG3/7 DIG3/2 DIG3/6 DIG3/1 DIG3/5 DIG3/0 DIG3/4

36 35 33 32 30 29 27 26

Dir4 Dir3
VCC

48 25 1 24 OE1 OE2 T/R1 T/R2

Dir9 Dir10 74ACTQ16245 C12 100n C9 100n

48 25 1 24 OE1 OE2 T/R1 T/R2

74ACTQ16245

B

DIG15/4 DIG15/0 DIG15/5 DIG15/1 DIG15/6 DIG15/2 DIG15/7 DIG15/3

47 46 44 43 41 40 38 37

A0 A1 A2 A3 A4 A5 A6 A7

B0 B1 B2 B3 B4 B5 B6 B7

2 3 5 6 8 9 11 12

BDIG15/4 BDIG15/0 BDIG15/5 BDIG15/1 BDIG15/6 BDIG15/2 BDIG15/7 BDIG15/3

B

U3
A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 2 3 5 6 8 9 11 12 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7

U6 BDIG6/3 BDIG6/7 BDIG6/2 BDIG6/6 BDIG6/1 BDIG6/5 BDIG6/0 BDIG6/4
47 46 44 43 41 40 38 37 2 3 5 6 8 9 11 12

DIG6/3 DIG6/7 DIG6/2 DIG6/6 DIG6/1 DIG6/5 DIG6/0 DIG6/4

47 46 44 43 41 40 38 37

DIG11/4 DIG11/0 DIG11/5 DIG11/1 DIG11/6 DIG11/2 DIG11/7 DIG11/3

BDIG11/4 BDIG11/0 BDIG11/5 BDIG11/1 BDIG11/6 BDIG11/2 BDIG11/7 BDIG11/3 Dir15

36 35 33 32 30 29 27 26

A8 A9 A1 A1 A1 A1 A1 A1

0 1 2 3 4 5

B8 B9 B10 B11 B12 B13 B14 B15

13 14 16 17 19 20 22 23

48 25 1 24

OE1 OE2 T/R1 T/R2

VCC

Figure B.3: F83 interface digital I/O 1 schematic
A8 A9 A1 A1 A1 A1 A1 A1 0 1 2 3 4 5 0 1 2 3 4 5 B8 B9 B10 B11 B12 B13 B14 B15 13 14 16 17 19 20 22 23 A8 A9 A1 A1 A1 A1 A1 A1 B8 B9 B10 B11 B12 B13 B14 B15

DIG5/3 DIG5/7 DIG5/2 DIG5/6 DIG5/1 DIG5/5 DIG5/0 DIG5/4
36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23

36 35 33 32 30 29 27 26

BDIG5/3 BDIG5/7 BDIG5/2 BDIG5/6 BDIG5/1 BDIG5/5 BDIG5/0 BDIG5/4

DIG12/4 DIG12/0 DIG12/5 DIG12/1 DIG12/6 DIG12/2 DIG12/7 DIG12/3

BDIG12/4 BDIG12/0 BDIG12/5 BDIG12/1 BDIG12/6 BDIG12/2 BDIG12/7 BDIG12/3

74ACTQ16245

C14 100n

Dir6 Dir5
VCC

48 25 1 24 OE1 OE2 T/R1 T/R2

Dir11 Dir12

48 25 1 24 OE1 OE2 T/R1 T/R2

VCC
Drawn: Date:

A

74ACTQ16245 C11 100n

74ACTQ16245 C10 100n

ATNF RECEIVER GROUP
Checked: Approved:

A

F83 Interface Board
Originator:

General Purpose Digital I/O
Issued: Schematic Filename:

K:\F83 PCB\Digital IO 1.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4 5 6 7

3
8

7

1

85


86

1

2

3

4

5

6

7

8

D

D

L1 R9 390R TXD L2 R10 390R LF24 L3 R11 390R REMOTE
B0 B1 B2 B3 B4 B5 B6 B7 SHGND 2 3 5 6 8 9 11 12 12 11 10 9 8 7 1 2 3 4 5 6 SHGND

U14 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8
47 46 44 43 41 40 38 37 A0 A1 A2 A3 A4 A5 A6 A7

ADDRESSED

U9 C15
VCC 8 VCC R0 1

NFA62R LF25 L4 R12 390R LOCAL
C

BDif1 DifDir1 FTX L5 NFA62R
SHGND

DIFA+ 100n
7 B A GND VCC DI 4 DE 3 RE 6 5 2

LED9 LED10 LED11 LED12
12 11 10 9 8 7 1 2 3 4 5 6

C

DIFAR13 390R EVENT L6 R15 180R R16 180R MISC
VCC SHGND

36 35 33 32 30 29 27 26 A8 A9 A1 A1 A1 A1 A1 A1 0 1 2 3 4 5 B8 B9 B10 B11 B12 B13 B14 B15

13 14 16 17 19 20 22 23

MAX487
VCC

U10
8 VCC B A GND DI 4 DE 3 RE 2 R0 1

48 25 1 24 OE1 OE2 T/R1 T/R2

R4 1K C16 BDif2 DifDir2 74ACTQ16245 100n
7 6 5

R14 390R

DIFB+ DIFBLF26 C17 100n PROG FRX
VCC VCC

R5 1K MAX487

SW1 SW-PB
5

12 11 10 9 8 7

1 2 3 4 5 6

U17 NFA62R
4 SHGND 2

R3 10K
1 3 2 4

U19

B

NC7S04
3

C18 100n

HFD3023

B

U20
1 3 4 2

Figure B.4: F83 interface digital I/O 2 schematic
HFE4074
Drawn: Date: Checked: Approved: Originator:

A

ATNF RECEIVER GROUP F83 Interface Board
Differential & Fibre I/O
Issued: Schematic Filename:

A

K:\F83 PCB\Digital IO 2.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4 5 6 7

4
8

7

APPENDIX B: F83 Interface Schematics

1


1 8

2

3

4

5

6

7

SHGND

SHGND

SHGND

SHGND

J1A
12

LF1

LF13

J1C

LF2

LF14
D

D

J1B1 J1A1 J1B2 J1A2 J1B3 ANALOG IN
SHGND SHGND SHGND

1 2 3 4 5 6

12 11 10 9 8 7

ANGND ANGND DIG1/4 DIG1/0 DIG1/5 J1D111 J1C110 J1D2 9 J1C2 8 J1D3 7 NFA62R LF4
SHGND 1 2 3 4 5 6

J1A18 1 J1B19 2 J1A19 3 J1B20 4 J1A20 5 J1B21 6
12 11 10 9 8 7

DIG5/2 DIG5/7 DIG5/3 DIG6/4 DIG6/0 DIG6/5
1 2 3 4 5 6 1 2 3 4 5 6

J1C112 8 J1D111 9 J1C110 9 J1D20 9 J1C208 J1D21 7 DIG12/2 DIG12/7 DIG12/3 DIG13/3 DIG13/0 DIG13/4

J1A3 J1B4 J1A4 J1B5 J1A5 J1B6
1 2 3 4 5 6

NFA62R LF3 12 DIG1/1 11 DIG1/6 10 DIG1/2 DIG1/7 9 DIG1/3 8 DIG2/4 7 J1A21 1 J1B22 2 J1A22 3 J1B23 4 J1A23 5 J1B24 6 DIG9/4 DIG9/0 DIG9/5 DIG9/1 DIG9/6
8 7 SHGND 12 SHGND SHGND

NFA62R LF15 12 DIG6/1 11 DIG6/6 10 DIG6/2 DIG6/7 9 DIG6/3 8 DIG7/4 7 J1C312 J1D411 J1C410 J1D5 9 J1C5 8 J1D6 7 J1C212 1 J1D211 2 J1C210 2 J1D23 9 NFA62R LF16 DIG13/1 1 DIG13/5 2 DIG13/2 3 GND 4 GND 5 GND 6

SHGND

J1A6 J1B7 J1A7 J1B8 J1A8 J1B9
1 2 3 4 5 6

NFA62R LF5 12 DIG2/0 11 DIG2/5 10 DIG2/1 DIG2/6 9 DIG2/2 8 DIG2/7 7 J1A24 1 J1B25 2 J1A25 3 J1B26 4 J1A26 5 J1B27 6 J1D211 5 J1C210 5 J1D26 9 J1C268 J1D27 7
SHGND SHGND SHGND

NFA62R LF17 12 DIG7/0 11 DIG7/5 10 DIG7/1 DIG7/6 9 DIG7/2 8 DIG7/7 7 J1C612 J1D711 J1C710 J1D8 9 J1C8 8 J1D9 7 NFA62R LF6 DIG9/2 1 DIG9/7 2 DIG9/3 3 DIG10/4 4 DIG10/0 5 DIG10/5 6 NFA62R LF18 GND 1 DIG14/3 2 DIG14/0 3 DIG14/4 4 DIG14/1 5 DIG14/5 6

J1C1 J1C2 J1C3 J1C4 J1C5 J1C6 J1C7 J1C8 J1C9 J1C10 J1C11 J1C12 J1C13 J1C14 J1C15 J1C16 J1C17 J1C18 J1C19 J1C20 J1C21 J1C22 J1D23

SHGND

C 3 10

1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11a 12a 13a 14a 15a 16a 17a 18a 19a 20a 21a 22a 23a 24a 25a 26a 27a 28a 29a 30a 31a 32a

J1A1 J1A2 J1A3 J1A4 J1A5 J1A6 J1A7 J1A8 J1A9 J1A10 J1A11 J1A12 J1A13 J1A14 J1A15 J1A16 J1A17 J1A18 J1A19 J1A20 J1A21 J1A22 J1A23 J1A24 J1A25 J1A26 J1A27 J1B28 J1A29 J1A30 J1A31 J1A32 J1A9 1 J1B102 J1A10 3 J1B114 J1A11 5 J1B126 J1A27 1 J1B28 2 J1B29 4 J1A29 5 J1B30 6 J1D29 9 J1C298 J1D30 7
SHGND

NFA62R LF7 12 DIG2/3 11 DIG3/4 10 DIG3/0 DIG3/5 9 DIG3/1 8 DIG3/6 7 J1C912 J1D111 0 J1C110 0 J1D11 9 J1C118 J1D12 7 J1C212 7 J1D211 8
SHGND

NFA62R LF19 12 DIG7/3 11 VCC 10 VCC DIFA+ 9 DIG8/0 8 DIFA7 NFA62R LF8 DIG10/1 1 DIG10/6 2 DIG10/2 3 DIG10/7 4 DIG10/3 5 DIG11/4 6 DIN128 J1D J1C312 0 J1D311 1 J1C310 1 J1D32 9 J1C328
7

1c 2c 3c 4c 5c 6c 7c 8c 9c 10c 11c 12c 13c 14c 15c 16c 17c 18c 19c 20c 21c 22c 23c 24c 25c 26c 27c 28c 29c 30c 31c 32c

J1C25 J1C26 J1C27 J1D28 J1C29 J1C30 J1C31 J1C32

NFA62R LF20 DIG14/2 1 GND 2 GND 3 DIG15/4 4 DIG15/0 5 DIG15/5 6

C

DIN128 J1B
SHGND SHGND

APPENDIX B: F83 Interface Schematics

J1A12 1 J1B132 J1A13 3 J1B144 J1A14 5 J1B156 J1A30 1 J1B31 2 J1A31 3 J1B32 4 J1A32 5
6 7

NFA62R LF9 12 DIG3/2 11 DIG3/7 10 DIG3/3 DIG4/2 9 DIG4/0 8 DIG4/3 7 J1C112 2 J1D111 3 J1C110 3 J1D14 9 J1C148 J1D15 7
SHGND

NFA62R LF21 12 DIG8/1 11 DIFB+ 10 DIG8/2 DIFB9 DIG8/3 8 NFA62R LF10 DIG11/0 1 DIG11/5 2 DIG11/1 3 DIG11/6 4 DIG11/2 5 DIG11/7 6 NFA62R

NFA62R LF22 DIG15/1 1 DIG15/6 2 DIG15/2 3 DIG15/7 4 DIG15/3 5
6

NFA62R
SHGND

SHGND

J1A15 1 J1B162 J1A16 3 J1B174 J1A17 5 J1B186 NFA62R
SHGND

NFA62R LF11 12 DIG4/1 11 DIG5/4 10 DIG5/0 DIG5/5 9 DIG5/1 8 DIG5/6 7
SHGND

J1C112 5 J1D111 6 J1C110 6 J1D17 9 J1C178 J1D18 7

NFA62R LF12 DIG11/3 1 DIG12/4 2 DIG12/0 3 DIG12/5 4 DIG12/1 5 DIG12/6 6 NFA62R
SHGND

B

1b 2b 3b 4b 5b 6b 7b 8b 9b 10b 11b 12b 13b 14b 15b 16b 17b 18b 19b 20b 21b 22b 23b 24b 25b 26b 27b 28b 29b 30b 31b 32b

J1B1 J1B2 J1B3 J1B4 J1B5 J1B6 J1B7 J1B8 J1B9 J1B10 J1B11 J1B12 J1B13 J1B14 J1B15 J1B16 J1B17 J1B18 J1B19 J1B20 J1B21 J1B22 J1B23 J1B24 J1B25 J1B26 J1B27 J1B28 J1B29 J1B30 J1B31 J1B32 J1D1 J1D2 J1D3 J1D4 J1D5 J1D6 J1D7 J1D8 J1D9 J1D10 J1D11 J1D12 J1D13 J1D14 J1D15 J1D16 J1D17 J1D18 J1D19 J1D20 J1D21 J1D22 J1D23 J1D25 J1D26 J1D27 J1D28 J1D29 J1D30 J1D31 J1D32
1d 2d 3d 4d 5d 6d 7d 8d 9d 10d 11d 12d 13d 14d 15d 16d 17d 18d 19d 20d 21d 22d 23d 24d 25d 26d 27d 28d 29d 30d 31d 32d

B

Figure B.5: F83 interface RFI filtering schematic
DIN128
Drawn: Date: Checked: Approved: Originator: Issued: Schematic Filename: Assembly Drawing No.:

DIN128

A

ATNF RECEIVER GROUP F83 Interface Board
DIN Connector and EMI Filters
K:\F83 PCB\Connector.sch
Revision: Sheet: Total:

A

5
2 3 4 5 6 7 8

7

1

87


88

APPENDIX B: F83 Interface Schematics

1

2

3

4

H +3V3

H

19 30 40 61 80 90 101 121 140 150 161 180 201 212 222 240

U12 XC5210PQ240 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 FTX BDif1 DifDir1 DifDir2 BDif2 FRX GND GND GND 3.6864MHz GND GND GND GND Dir8 BDIG8/3 BDIG8/2 BDIG8/1 BDIG8/0 BDIG7/3 BDIG7/7 BDIG7/2 BDIG7/6 BDIG7/1 BDIG7/5 BDIG7/0 BDIG7/4 Dir7 BDIG15/3 BDIG15/7 BDIG15/2 BDIG15/6 BDIG15/1 BDIG15/5 BDIG15/0 BDIG15/4 Dir15 Dir5 BDIG5/4 BDIG5/0 BDIG5/5 BDIG5/1 BDIG5/6 BDIG5/2 BDIG5/7 BDIG5/3 BDIG6/4 BDIG6/0 BDIG6/5 BDIG6/1 BDIG6/6 BDIG6/2 BDIG6/7 BDIG6/3 Dir6 Dir14
VCC 179 177 178 122 120 89 68 64 62 58 60 6 181 7 17

G

F

E

D

BDIG14/2 BDIG14/5 BDIG14/1 BDIG14/4 BDIG14/0 BDIG14/3 BDIG13/2 BDIG13/5 BDIG13/1 BDIG13/4 BDIG13/0 BDIG13/3 Dir13 Dir4 BDIG4/1 BDIG4/3 BDIG4/0 BDIG4/2 BDIG3/3 BDIG3/7 BDIG3/2 BDIG3/6 BDIG3/1 BDIG3/5 BDIG3/0 BDIG3/4 Dir3 Dir12 BDIG12/3 BDIG12/7 BDIG12/2 BDIG12/6 BDIG12/1 BDIG12/5 BDIG12/0 BDIG12/4 BDIG11/3 BDIG11/7 BDIG11/2 BDIG11/6 BDIG11/1 BDIG11/5 BDIG11/0 BDIG11/4 Dir11 Dir2 BDIG2/3 BDIG2/7 BDIG2/2 BDIG2/6 BDIG2/1 BDIG2/5 BDIG2/0 BDIG2/4 BDIG1/3 BDIG1/7 BDIG1/2 BDIG1/6 BDIG1/1 BDIG1/5 BDIG1/0 BDIG1/4 Dir1 Dir10 BDIG10/3 BDIG10/7 BDIG10/2 BDIG10/6 BDIG10/1 BDIG10/5 BDIG10/0 BDIG10/4 BDIG9/3 BDIG9/7 BDIG9/2 BDIG9/6 BDIG9/1 BDIG9/5 BDIG9/0 BDIG9/4 Dir9 HIGH AnST AnBSY

C

D0 D1 D2 D3 D4 D5 D6 D7 ROMEN ROMRD ROMWR A0

2 3 4 5 8 9 10 11 12 13 15 16 18 20 21 23 24 25 26 27 28 31 32 33 34 35 36 38 39 41 42 43 44 46 47 48 49 50 51 52 53 54 55 56 57 63 65 66 67 69 70 71 72 73 74 76 77 78 79 81 82 84 85 86 87 88 92 93 94 95 96 97 99 100 102 103 104 105 107 108 109 110 111 112 113 114 115 116 117 118 123 124 125 126 127 128 129 130 131 132

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

GCLK1-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK2-I/O GCLK3-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK4-I/O I/O GCLK5-I/O I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK7-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK8-I/O CCLK DIN-I/O DOUT-GCLK6-I/O PROG DONE INIT-I/O LDC-I/O HDC-I/O PW RDW N M1 M0 TDI-I/O TDO-O TCK-I/O TMS-I/0

133 134 136 137 138 139 141 142 144 145 146 147 148 149 152 153 154 155 156 157 159 160 162 163 164 165 167 168 169 170 171 172 173 174 175 176 183 184 185 186 187 188 189 190 191 192 193 194 197 198 199 200 202 203 205 206 207 208 209 210 213 214 215 216 217 218 220 221 223 224 225 226 228 229 230 231 232 233 234 235 236 237 238 239

+3V3

G

C19 100n

C20 100n

C21 100n

C22 100n

C26 100n

C27 100n

C28 100n

C29 100n

C23 100n

C25 100n

VCC

F

VCC

TP4
1

VCC TP5
1

GND
E

U13 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 ROMEN ROMRD ROMWR
12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE WE

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC NC

13 14 15 17 18 19 20 21 30 1

D0 D1 D2 D3 D4 D5 D6 D7

D

AM29F010-120JC(32)

CCLK DIN PROG DONE AnEN
+3V3

R7 4K7 INIT

C

+3V3 +3V3

R18 4K7 JP1 DIN CCLK

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

20

R19 4K7 U15 AT17LV010
SEREN CEO 17 18 5 7

VCC

+3V3

R17 4K7

B

CCLK DIN DONE INIT PROG

4 2 8 6 15

1 14 22 29 37 45 59 75 83 98 106 91 119 135 143 151 158 166 182 196 204 211 219 227

D CE RST RDY

VCC

2 4 6 8 10

1 3 5 7 9

1N4148 D5

HEADER 5X2
B

GND

WP1 WP2

PROG LF23 NFM40R
8

C30 100n U16 LF28 NFM40R 3.6864MHz

VCC

OUT

5

10

VCC

GND

Drawn:

Date:

ATNF RECEIVER GROUP F83 Interface Board
A

Checked:

3.6864MHz OSCILLATOR

4

Approved:

A
Originator:

Xilinx Chip and support
Schematic Filename:

Issued:

K:\F83 PCB\Xilinx 1.sch
Revision: Sheet: Total:

Assembly Drawing No.:

1.0
1 2 3 4

6

7

Figure B.6: F83 interface Xilinx support schematic


1

2

3

4

D

D

+5V

VCC

L7
3 VIN VOUT 5

D1 TMMBAT-48 C34 47u 16V
SPG 8 SC
GND

U11 ZLD0330
+3V3

C

100uH C33 10u 10V
4 LBF 1

C

APPENDIX B: F83 Interface Schematics

C32 10u 10V

C36 10p C35 2u2 10V C31 100n

VSS

C3
SHGND

100n

Figure B.7: F83 interface power supply schematic
7
Drawn: Date: Checked: Approved: Originator: Issued: Schematic Filename: Assembly Drawing No.:

B

B

ATNF RECEIVER GROUP F83 Interface Board
A

A

3V3 Power Supply
K:\F83 PCB\Power Supply.sch
Revision: Sheet: Total:

1.0
2 3 4

7

7

1

89


90

APPENDIX B: F83 Interface Schematics

1

2

3

4

D

D

comms comms.sch

locprts locprts.sch

address address.sch

adc adc.sch

C

addbuss addbuss.sch

trancver trancver.sch

C

B

B

U2 VCC 1 0
Drawn: Date:

ATNF RECEIVER GROUP F83/F33 Replacement Xilinx
A

U1 GND
A

Checked:

Approved:

Originator:

Project Sheet
Schematic Filename:

XILINX PARTTYPE=XCS40XLPQ240-5

Issued:

K:\F83_mm\F83_mm.prj
Revision: Sheet: Total:

Assembly Drawing No.:

1
1 2 3 4

7

Figure B.8: F83 interface Xilinx pro ject sheet


1

2

3

4

P170

U9

DIF1

D

OBUFE U38 U33 15Hz 1 1 U39 OEN U41 INV
E

P174 BRXD U17 INV
RXD TXD

U15 U34

RXD BRXD INV CB2CE

IPAD OEN E U19
TXD_EN

IBUF

U3

P169 15Hz STB CB2CE U61 OEN U35 INV 1 1 WR STB HBE 15Hz PAR CB2CE U64 U60 INV
Q0 Q1 CEO TC CE C CLR CE C CLR Q0 Q1 CEO TC

TXD U18 M2_1 IBUF U7 3_6864MHZ
CLK WR STB HBE

OPAD

P173 PAR ERR
PAR ERR

DIF2

IPAD

C

P184 BUFG U10 OEN E 0 OBUFE U14 OEN E 1 OBUFE 15Hz ERR

CLK

IPAD

APPENDIX B: F83 Interface Schematics

P172

DIFDIR2

DSA = 0/1

OPAD

P171

DIFDIR1

38400 BPS

OPAD

B

U12 U258 U16 PORST INV OSC4 500KHz

Figure B.9: F83 interface Xilinx comms schematic
U42 U40 INV
CE C CLR I3 I2 I1 I0 O3 O2 O1 O0 Q0 Q1 CEO TC

3_6864MHZ

0

CE C CLR

Q0 Q1 Q2 Q3 CEO TC F8M F500K F16K F490 F15

CB4CE

A

Power on Reset

1

D0 D1 S0

O

OBUFE

E
OEN
ADD<0> ADD<1> ADD<2> ADD<3> ADD<4> ADD<5> ADD<6> ADD<7> ADD<8> ADD<9> CE C CLR Q0 Q1 CEO TC

OPAD

D

P159 OPAD P160 OPAD P162 OPAD P163 OBUFE4 OPAD

LED5

TXD
LED6

LED7

Busy
LED8

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 U65
E

P164 OPAD P165 OPAD P167 OBUFE4 OPAD P168 OPAD

LED9

Parity
LED10

C

I0 I1 I2 I3

O0 O1 O2 O3

LED11

0 0 0 0
DSA<1> DSA<2> DSA<3> DSA<4>

Error
LED12

1 1 0 1
BAUD<0> BAUD<1> BAUD<2> BAUD<3>

CB2CE

Status LED Drivers
B

PORST
RST

DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15>

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

DATASET2

Dataset State Machine

P89 IPAD

U264 OEN IBUF

15Hz

Drawn:

Date:

ATNF RECEIVER GROUP
Checked: Approved:

Clock Divider
Originator: Schematic Filename: Issued:

F83 MM Receiver Xilinx
A

Dataset Comms
K:\F83_mm\comms.sch
Assembly Drawing No.: Revision: Sheet: Total:

2
2 3 4

7

91


92

1

2

3

4

D

D

U156 A0 A1 A2 A3
A0 A1 A2 A3 A0 A1 A2 A3

U54 A4 A5 A6 A7

U266 STB INV WCK

0-15 16-31 32-47 48-63 64-95 96-111 112-127 128-143

C

C

U4 0-15 WR A8 D4_16E AND2B1 U255 U5 A9 ANEN WR AND2B2 A0 A1 A2 A3
A0 A1 A2 A3 E E

U36 A9

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

Read0 Read1 Read2 Read3 Read4 Read5 Read6 Read7 Read8 Read9 Read10 Read11 Read12 Read13 Read14 Read15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

D4_16E AND2B1

B

B

U53 0-15 WR D4_16E AND2
E

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

Write0 Write1 Write2 Write3 Write4 Write5 Write6 Write7 Write8 Write9 Write10 Write11 Write12 Write13 Write14 Write15

Address Decoder

Figure B.10: F83 interface Xilinx address decode schematic
Drawn: Date: Checked: Approved:

ATNF RECEIVER GROUP F83 MM Receiver Xilinx
A
Originator:

A

Address Decoding
Issued: Schematic Filename:

K:\F83_mm\address.sch
Assembly Drawing No.: Revision: Sheet: Total:

3
2 3 4

7

APPENDIX B: F83 Interface Schematics

1


1

2

3

4

D

D

P72 DIG2/0 OPAD P104 DIG9/1 U27 OEN
E

OPAD P70 DIG2/1 OPAD P102 DIG9/2 OPAD P99 DIG9/3 OPAD P67 DIG2/2 OPAD P73 DIG2/4 OPAD P71 OPAD P69 OPAD

APPENDIX B: F83 Interface Schematics

C

C

A0 A1 A2 A3 A4 A5 A6 A7
I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7

ANALOG MUX ADDRESS

OBUFE8 U13 A8 OEN OBUFE

Figure B.11: F83 interface Xilinx address buss schematic
2

B

A
Originator:

1

E

DIG2/5

DIG2/6
B

Drawn:

Date:

ATNF RECEIVER GROUP
Checked: Approved:

F83 MM Receiver Xilinx
A

Address Buss
Issued: Schematic Filename:

K:\F83_mm\addbuss.sch
Assembly Drawing No.: Revision: Sheet: Total:

4
3 4

7

93


94

APPENDIX B: F83 Interface Schematics

1

2

3

4

MON5-0

P191 IPAD P193 IPAD P198 IPAD P203 IPAD P200 IPAD P194 IPAD P192 IPAD P190 IPAD

DIG8/2

MON6-0

P207 IPAD P209 IPAD P213 IPAD P215 IPAD P205 IPAD P202 IPAD P199 IPAD P197 IPAD

DIG15/3

MON5-1
H

DIG8/0 U23 DIG7/2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 E I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

MON6-1 Read6 U21
O0 O1 O2 O3 O4 O5 O6 O7 I0 I1 I2 I3 I4 I5 I6 I7

DIG15/2
H

U48
E

Read5 U44
O0 O1 O2 O3 O4 O5 O6 O7 I0 I1 I2 I3 I4 I5 I6 I7

MON5-2

MON6-2

DIG15/1

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
G

O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

MON5-3

DIG7/0 MON 5 INPUTS DIG7/1

MON6-3

DIG15/0 MON 6 INPUTS DIG7/4

MON5-4

MON6-4

MON5-5

DIG7/3

MON6-5

DIG7/5

IBUF8 MON5-6

IBUF8 MON6-6

DIG8/1

DIG7/6

MON5-7

DIG8/3

MON6-7

DIG7/7
G

BUFE16 U11 GND MON7-0

BUFE16 U22 GND DIG14/0 MON8-0

P8 IPAD P4 IPAD P2 IPAD P9 IPAD P5 IPAD P3 IPAD P216 IPAD P214 IPAD

P56 IPAD P54 IPAD P52 IPAD P50 IPAD P48 IPAD

DIG11/4

MON7-1 U45
E

DIG14/1 U46 DIG14/2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 E I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

MON8-1 Read8 U43
O0 O1 O2 O3 O4 O5 O6 O7 I0 I1 I2 I3 I4 I5 I6 I7

DIG11/5

Read7 U37
O0 O1 O2 O3 O4 O5 O6 O7 I0 I1 I2 I3 I4 I5 I6 I7

MON7-2

MON8-2

DIG11/6

MON 8 INPUTS

F

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

MON7-3

DIG14/3 MON 7 INPUTS DIG14/4

MON8-3

DIG11/7

MON7-4

MON8-4

DIG12/4
F

MON7-5

DIG14/5

IBUF8 MON7-6

IBUF8

DIG15/4

MON7-7

DIG15/5

BUFE16 U24 GND

BUFE16 U25 GND

E

MON9-0

P55 IPAD P53 IPAD P51 IPAD P49 IPAD P47 IPAD P44 IPAD P42 IPAD P39 IPAD

E

DIG11/0 P220 OPAD P223 OPAD P225 OPAD P228 OPAD P230 OPAD P232 OPAD P234 OPAD P236 OPAD

MON9-1 U57
E

DIG11/1

CMD3-0

DIG5/4

Read9 U55
O0 O1 O2 O3 O4 O5 O6 O7 I0 I1 I2 I3 I4 I5 I6 I7

MON9-2

DIG11/2 U30 OEN DIG11/3 MON 9 INPUTS DIG12/0 D0 D1 D2 D3 D4 D5 D6 D7 Write3 WCK 0 U51
D0 D1 D2 D3 D4 D5 D6 D7 CE C CLR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E

CMD3-1

DIG5/5

D

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

MON9-3

CMD3-2
O0 O1 O2 O3 O4 O5 O6 O7

DIG5/6

MON9-4

MON9-5

DIG12/1

IBUF8 MON9-6

C30 C31 C32 C33 C34 C35 C36 C37

DIG12/2

I0 I1 I2 I3 I4 I5 I6 I7

CMD3-3

DIG5/7 CMD 3 OUTPUTS DIG6/4

CMD3-4

CMD3-5

DIG6/5

OBUFE8 CMD3-6 DIG6/6

D

MON9-7

DIG12/3

BUFE16 U52 GND

FD8CE U49 Read3
E

CMD3-7

DIG6/7

C

CMD2-0

P226 OPAD P224 OPAD P231 OPAD P229 OPAD P235 OPAD P233 OPAD P221 OPAD P237 OPAD

DIG5/2

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

CMD2-1 U29 OEN U50 D0 D1 D2 D3 D4 D5 D6 D7 Write2 WCK 0
D0 D1 D2 D3 D4 D5 D6 D7 CE C CLR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E

DIG5/1

O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

C30 C31 C32 C33 C34 C35 C36 C37

C

BUFE16 DIG6/0 U28 GND

CMD2-2
O0 O1 O2 O3 O4 O5 O6 O7

C20 C21 C22 C23 C24 C25 C26 C27

I0 I1 I2 I3 I4 I5 I6 I7

CMD2-3

DIG5/3 CMD 2 OUTPUTS DIG6/2

CMD2-4

CMD2-5

DIG6/1
B

OBUFE8 CMD2-6 DIG5/0

B

FD8CE U47 Read2
E

CMD2-7

DIG6/3

A

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

C20 C21 C22 C23 C24 C25 C26 C27

Drawn:

Date:

ATNF RECEIVER GROUP
A

Checked:

Approved:

Originator:

Local Ports
Schematic Filename:

Issued:

K:\F83_mm\locprts.sch
Revision: Sheet: Total:

BUFE16 U26 GND
1 2 3

Assembly Drawing No.:

5
4

7

Figure B.12: F83 interface Xilinx local ports schematic


1

2

3

4

D

D

XR2 PULLUP XR3 PULLUP FD0 D0 XR4 PULLUP U20 ANEN STB
ADCRQ STB

P117 IPAD P118 D1 IPAD P123 D2 IPAD P124 IPAD P125 IPAD P126 IPAD P127

U56 XR5 PULLUP FD2 XR6 PULLUP FD3 XR7 PULLUP FD4 XR8 PULLUP OEN XR9 PULLUP FD6 OBUFE OEN U62 E OBUFE OEN U6 E OBUFE U8 FD7 XR11 PULLUP XR12 PULLUP XR13 PULLUP XR10 PULLUP U63 E FD5 D3

FD1

C

ADCDATA<0> ADCDATA<1> ADCDATA<2> ADCDATA<3> ADCDATA<4> ADCDATA<5> ADCDATA<6> ADCDATA<7>

O0 O1 O2 O3 O4 O5 O6 O7

I0 I1 I2 I3 I4 I5 I6 I7

FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 D4

C

IBUF8
ADCEN ANST ANHIGH BUSY

APPENDIX B: F83 Interface Schematics

D5

D6 IPAD P128 IPAD P64 OPAD P111

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15> CLK RST

D7

3_6864MHZ PORST ADCRD16

AnEN

AnST OPAD P110 OPAD P112
B

B

HIGH

AnBSY IBUF IPAD

ADC Sequencing

Figure B.13: F83 interface Xilinx ADC sequencing schematic
Drawn: Date: Checked: Approved: Originator: Issued: Schematic Filename:

ATNF RECEIVER GROUP F83 MM Receiver Xilinx
A

A

ADC Control & ADC Scaling
K:\F83_mm\adc.sch
Assembly Drawing No.: Revision: Sheet: Total:

6
2 3 4

7

1

95


96

1

2

3

4

D

D

U31 OEN
E

P85 DIR1 - INPUT OPAD P63 DIR2 - OUTPUT OPAD P36 DIR3 - INPUT OPAD P20 DIR4 - INPUT OPAD P218 DIR5 - OUTPUT OPAD P238 DIR6 - OUTPUT OPAD P206 DIR7 - INPUT OPAD P189 DIR8 - INPUT OPAD P109 DIR9 - OUTPUT OPAD P86 DIR10 - INPUT OPAD P57 DIR11 - INPUT OPAD P38 DIR12 - INPUT OPAD P18 OPAD P239 OPAD P217 OPAD
Drawn: Date:

1 0 1 1 0 0 1 1
I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7

OBUFE8

C

C

U32 OEN
E

B

0 1 1 1 1 1 1 1
I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7

B

OBUFE8

DIR13 - INPUT

DIR14 - INPUT

DIR15 - INPUT

ATNF RECEIVER GROUP
Checked: Approved:

Figure B.14: F83 interface Xilinx transceiver direction schematic
F83 MM Receiver Xilinx
A
Originator:

A

Tranceiver direction setup
Issued: Schematic Filename:

K:\F83_mm\trancver.sch
Assembly Drawing No.: Revision: Sheet: Total:

7
2 3 4

7

APPENDIX B: F83 Interface Schematics

1


App endix C WVR Interface Schematics

1

2

3

4

ADC 1.sch
D

DAC 1.sch
D

Connector.sch

Xilinx 1.sch

Digital IO 1.sch

Power Supply.sch

C

C

B

B

Drawn:

Date:

ATNF RECEIVER GROUP WVR Interface Board
A

Checked:

Approved:

A
Originator:

Project Sheet
Schematic Filename:

Issued:

K:\W VR PCB\W VR main.prj
Revision: Sheet: Total:

Assembly Drawing No.:

1.0
1 2 3 4

1

7

Figure C.1: WVR interface pro ject sheet

97


98

1

2

3

4

+15V

1

U16
V+

MUX_A_EN
18 EN A0 A1 A2 COMA 28 17 16 15

D

MUX_A0 MUX_A1 MUX_A2 AN+

D

+15V

C32
+15V +5V

ANI0+ ANI1+ ANI2+ ANI3+ ANI4+ ANI5+ ANI6+ ANI7+
19 20 21 22 23 24 25 26 N1A N2A N3A N4A N5A N6A N7A N8A

100n 25V
7 7

2

ANAN+
2 2 1 6 8 6 3 2 1

U18 AD620
8

COMB

U21 R6 30K1 0.1% OP-177
4 1

3

U22
+VDD

+VIN -VIN VREF

CLK DOUT
GND

4 5 6 SCLK

ADC_CLK ADC_DOUT ADC_SCLK
C

C
VGND

ANI0ANI1ANI2ANI3ANI4ANI5ANI6ANI711 10 9 8 7 6 5 4 N1B N2B N3B N4B N5B N6B N7B N8B

AN3
4 5

8

MAX307CWI
27 12

2V5REF 100n 25V
-15V +15V

-15V R7 10K0 0.1%

-15V +15V

C31
1

U20 U17
2 VIN VOUT NR TRIM GND 5 6 3

EN

V+

MUX_B_EN
18

470n 25V C21 1u 10V
4

B

MUX_A0 MUX_A1 MUX_A2
17 16 15 A0 A1 A2

C29 3u3 10V

7

C33

C20 100n

ADS1252

MAX6325
COMA 28

B

V-

N1B N2B N3B N4B N5B N6B N7B N8B
GND

27

12

Figure C.2: WVR interface ADC schematic
ANI8+ ANI9+ ANI10+ ANI11+ ANI12+ ANI13+ ANI14+ ANI15+
19 20 21 22 23 24 25 26 N1A N2A N3A N4A N5A N6A N7A N8A COMB 2

AN+

AN-

Drawn:

Date:

ATNF RECEIVER GROUP
Checked: Approved:

ANI8ANI9ANI10ANI11ANI12ANI13ANI14ANI1511 10 9 8 7 6 5 4

WVR Interface Board
A
Originator:

A

MAX307CWI

ADC
Issued: Schematic Filename:

K:\W VR PCB\ADC 1.sch
Assembly Drawing No.: Revision: Sheet: Total:

-15V

1.0
2 3 4

2

7

APPENDIX C: WVR Interface Schematics

1


1

2

3

4

D SHGND SHGND

D

SHGND

J1A LF8
12 11 10 9 8 7

J1B

LF5 FDIFA+ FDIFAFDIFB+ FDIFBFDIFGND FDIFGND
1 2 3 4 5 6 12 11 10 9 8 7 1 2 3 4 5 6 12 11 10 9 8 7

LF12 FANI9+ FANI9FANI10+ FANI10FANI11+ FANI11DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 NFA62R
SHGND

DIFA+ DIFADIFB+ DIFBGND GND NFA62R
SHGND

1 2 3 4 5 6

ANI9+ ANI9ANI10+ ANI10ANI11+ ANI11FDIG2 FDIG3 FDIG4 FDIG5 FDIG6 FDIG7

NFA62R

SHGND

LF3

LF9

LF13

C

ANI0+ ANI0ANI1+ ANI1ANI2+ ANI212 11 10 9 8 7

1 2 3 4 5 6

FANI0+ FANI0FANI1+ FANI1FANI2+ FANI21 2 3 4 5 6 12 11 10 9 8 7 1 2 3 4 5 6 12 11 10 9 8 7

ANI12+ ANI12ANI13+ ANI13ANI14+ ANI14FANI12+ FANI12FANI13+ FANI13FANI14+ FANI14DIG8 DIG9 DIG10 DIG11 DIG12 DIG13 FDIG8 FDIG9 FDIG10 FDIG11 FDIG12 FDIG13 NFA62R
SHGND

C

NFA62R
SHGND

NFA62R

SHGND

APPENDIX C: WVR Interface Schematics

LF4
12 11 10 9 8 7

LF10 FANI3+ FANI3FANI4+ FANI4FANI5+ FANI51 2 3 4 5 6 12 11 10 9 8 7 1 2 3 4 5 6 12 11 10 9 8 7

LF14 FANI15+ FANI15FANO0+ FANO0FANO1+ FANO1NFA62R
SHGND

ANI3+ ANI3ANI4+ ANI4ANI5+ ANI5DIG14 DIG15 GND GND GND GND NFA62R
SHGND

1 2 3 4 5 6

ANI15+ ANI15ANO0+ GND ANO1+ GND FDIG14 FDIG15 FGND FGND FGND FGND

FANI0+ FANI1+ FANI2+ FANI3+ FANI4+ FANI5+ FANI6+ FANI7+ FANI8+ FANI9+ FANI10+ FANI11+ FANI12+ FANI13+ FANI14+ FANI15+ FANO0+ FANO1+ FANO2+ FANO3+ FDIG0 FDIG2 FDIG4 FDIG6 FDIG8 FDIG10 FDIG12 FDIG14 FGND FGND F+20V

FANI0FANI1FANI2FANI3FANI4FANI5FANI6FANI7FANI8FANI9FANI10FANI11FANI12FANI13FANI14FANI15FANO0FANO1FANO2FANO3FDIG1 FDIG3 FDIG5 FDIG7 FDIG9 FDIG11 FDIG13 FDIG15 FGND FGND F-20V DIN64

NFA62R

SHGND

1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11a 12a 13a 14a 15a 16a 17a 18a 19a 20a 21a 22a 23a 24a 25a 26a 27a 28a 29a 30a 31a 32a

1c 2c 3c 4c 5c 6c 7c 8c 9c 10c 11c 12c 13c 14c 15c 16c 17c 18c 19c 20c 21c 22c 23c 24c 25c 26c 27c 28c 29c 30c 31c 32c

LF7

LF11

LF15

DIN64
B

B

J2 FDIFA+ FDIFAFDIFB+

ANI6+ ANI6ANI7+ ANI7ANI8+ ANI812 11 10 9 8 7

1 2 3 4 5 6

FANI6+ FANI6FANI7+ FANI7FANI8+ FANI81 2 3 4 5 6 12 11 10 9 8 7 1 2 3 4 5 6 12 11 10 9 8 7

ANO2+ GND ANO3+ GND DIG0 DIG1 FANO2+ FANO2FANO3+ FANO3FDIG0 FDIG1 FGND FGND F+20V F+20V F-20V F-20V NFA62R
SHGND

GND GND +20V +20V -20V -20V

NFA62R
SHGND

NFA62R

SHGND

FDIFBFDIFGND

Figure C.3: WVR interface RFI filtering schematic
Drawn: Date: Checked: Approved: Originator:

1 6 2 7 3 8 4 9 5

DB9

ATNF RECEIVER GROUP WVR Interface Board
A

A

RFI Filtering
Issued: Schematic Filename:

K:\W VR PCB\Connector.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

3

7

1

99


100

1

2

3

4

D

D

U8 C14
VCC 8 VCC B A GND DI 4 DE 3 RE 2 R0 1

BDif1 DifDir1
C

DIFA+
7 6 5

100n

C

DIFA-

MAX487
VCC

U11
8 VCC B A GND DI 4 DE 3 RE 2 R0 1

C15 BDif2 DifDir2

DIFB+
7 6 5

100n

DIFB-

MAX487
B

Figure C.4: WVR interface digital I/O schematic
Drawn: Date: Checked: Approved: Originator:

B

ATNF RECEIVER GROUP WVR Interface Board
A

A

Digital I/O 1
Issued: Schematic Filename:

K:\W VR PCB\Digital IO 1.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

4

7

APPENDIX C: WVR Interface Schematics

1


1 +15V

2

3

4

DACA
3 + 1 + 7 5 2 6 -

4

U24A LM837 U24B LM837 R28 ANO0+ 120R R24 30K 0.1%
-15V

D

D

2V5REF 10K 0.1% 10K 0.1%

R8 R10 10K 0.1%

R9

+5V

C30

2u2 DACB
10 + 8 + 14 12 9 13 -

20

11

U24C LM837 U24D LM837 R29 ANO1+ 120R

U23
OUTA FBA 3 2

C

VDD

DACA

DACB R25 30K 0.1% DACC 2V5REF 10K 0.1% 10K 0.1%
+15V

DACRS DACCS DACDI DACCK DACDO
OUTB FBB OUTC FBC 17 16 4 5

7 8 9 10 12 13 14

CL CS DIN SCLK DOUT UPO PDL

C

R11 R13 10K 0.1%

R12

APPENDIX C: WVR Interface Schematics

DGND

REFAB REFCD

AGND

2V5REF
OUTD FBD 18 19

6 15

DACD

MAX525
4

11

1

DACC
3 + 1 + 7 6
11

U25A LM837
5

U25B LM837 R30

2 -

ANO2+ 120R

R26
B

B -15V

30K 0.1% R20 10K 0.1%

2V5REF 10K 0.1% 10K 0.1%

Figure C.5: WVR interface DAC schematic
R14 R16 DACD
10 + 9

U25C LM837
8 12 13 + -

U25D LM837
14

R31 120R R27 30K 0.1%

ANO3+
Drawn: Date:

ATNF RECEIVER GROUP
Checked: Approved:

WVR Interface Board
R22 10K 0.1%
A

A

2V5REF

R21 10K 0.1%

R23 10K 0.1%

Originator:

DAC 1
Issued: Schematic Filename:

K:\W VR PCB\DAC 1.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

5

7

101

1


102

APPENDIX C: WVR Interface Schematics

1

2

3

4

VCC D +3V3

LF1 NFM40R
4

C10 100n U19 LF2 NFM40R 3_6864MHz

D

18 37 54 73 90 108 128 144

U7
C C C C C C C C

OSCEN
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK7-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK8-I/0 CCLK DIN-I/O DOUT-GCLK6-I/O PROG DONE INIT-I/O LDC-I/O HDC-I/O PWRDWN M1 M0 TDI-I/O TDO-O TCK-I/O TMS-I/0 86 87 88 89 92 93 94 95 96 97 98 99 101 102 103 104 111 112 113 114 115 116 117 119 120 121 122 123 124 125 126 129 130 131 132 133 134 135 136 138 139 140 141 142 143 107 105 106 74 72 53 44 40 38 34 36 6 109 7 11

1

VCC

VC VC VC VC VC VC VC VC

EN

OUT

3

C

B

BDif2 DifDir2 BDif1 DifDir1 DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG9 DIG8 DIG7 DIG6 DIG5 DIG4 DIG3 DIG2 DIG1 DIG0

2 3 4 5 9 10 12 13 14 15 16 19 20 21 22 23 24 25 26 28 29 30 31 32 33 39 41 42 43 46 47 48 49 50 51 52 56 57 58 59 60 61 62 63 65 66 67 68 69 70 75 76 77 78 79 80 82 83 84 85

GCLK1-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK2-I/O GCLK3-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK4-I/O I/O GCLK5-I/O I/O I/O I/O I/O I/O I/O I/O I/O

GND

ECS3951C
2

DACDO DACRS DACCS DACDI DACCK MUX_A0 MUX_A1 MUX_A2 MUX_A_EN MUX_B_EN ADC_CLK ADC_DOUT ADC_SCLK

C

+3V3 +3V3 +3V3

+3V3

R3 4K7 CCLK DIN DONE INIT PROG
4 2 8 6 15

20

R4 4K7 U26 AT17LV010
SEREN CEO 17 18 5 7

R1 4K7

D CE RST RDY

GND 10

VCC

WP1 WP2

3_6864MHz
VCC

CCLK DIN PROG DONE R5 4K7 INIT C16 100n C17 100n C18 100n

+3V3 B

C19 100n

GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN

D D D D D D D D D D D D D D D D

XCS20XLTQ144
1 8 17 27 35 45 55 64 71 81 91 100 110 118 127 137
A

Drawn:

Date:

ATNF RECEIVER GROUP WVR Interface
Xilinx Support
Schematic Filename:

A

Checked:

Approved:

Originator:

Issued:

K:\W VR PCB\Xilinx 1.sch
Revision: Sheet: Total:

Assembly Drawing No.:

1.0
1 2 3

6
4

7

Figure C.6: WVR interface Xilinx support schematic


1

2

3

4

D

D

U2 MC7805T
VCC 3 VIN VOUT 3 5 VCC

U5 ZLD0330
+3V3

+20V
1 Vin +5V

GND

C
2

C3 1u 10V
SPG 8 SC
GND

C9 100n
4 LBF 1

C7 10p

C8 1u 10V

C

APPENDIX C: WVR Interface Schematics

U13 LM78L15ACM
+15V 1 Vin
GND GND GND GND

U14 LM78L05ACM
+5V 1 8 +5

8 Vin
GND GND GND GND

+5

C1 4u7 25V
2 3 6 7 2 3 6 7

C4 470n 25V

C6 1u 10V

B

7

B -15V 1

U3 LM79L15ACM -20V
-5
GND

C2 4u7 25V
5

Figure C.7: WVR interface power supply schematic
2 3 6 7 Vi Vi Vi Vi n n n n

C5 470n 25V

Drawn:

Date:

ATNF RECEIVER GROUP
Checked: Approved:

WVR Interface
A
Originator:

A

Power Supply
Issued: Schematic Filename:

K:\W VR PCB\Power Supply.sch
Assembly Drawing No.: Revision: Sheet: Total:

B
2 3 4

7

7

103

1


104

1

2

3

4

P59 BRXD
RXD TXD

U15 U17

RXD U22 A4 U13 ANE AND2B1 U25 WR INV
D

IPAD
TXD_EN

IBUF

P57

U3

D

TXD

OPAD PAR ERR
PAR ERR WR STB

OBUF WR STB A4 AND2 U24
E

ADD<0> ADD<1> ADD<2> ADD<3> ADD<4> ADD<5> ADD<6> ADD<7> ADD<8>

A0 A1 A2 A3 A4 A5 A6 A7 A8

P143 3_6864MHZ
CLK

U7

CLK

IPAD

BUFG

P58

U10

DSA = 2
MUXADD<0> MUXADD<1>

OPAD

0 1 0 0 0
DSA<0> DSA<1> DSA<2> DSA<3> DSA<4>

U23

U18

U4

P116 OBUF U5 U6 OBUF OBUF U19 OPAD P117 OPAD P119
C

OBUF

P60

U14

0

115200 BPS

C

OPAD BUFE8
CE C CLR

1 1 0 0
BAUD<0> BAUD<1> BAUD<2> BAUD<3>

OBUF PORST
RST

D0 D1 D2 D3 D4 D5 D6 D7
O0 O1 O2 O3 O4 O5 O6 O7 MUXADD<2> MUX1EN I0 I1 I2 I3 I4 I5 I6 I7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7

DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15>

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 U20
MUX2EN

OPAD P120 OBUF OBUF U8
ADCCLK

DATASET

OPAD P121 OPAD P122 U9
ADCSCLK

Dataset State Machine
0 ANE INV STB

FD8CE U21

OBUF OBUF U11
ADCDATA

OPAD P124 OPAD P123 IBUF A0 A1 A2 A3
ANE STB ADD<0> ADD<1> ADD<2> ADD<3> CLK RST

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15> DATA<16> DATA<17> DATA<18> DATA<19> DATA<20> DATA<21> DATA<22> DATA<23>

IPAD ANE STB 3_6864MHz PORST WVRADC24
B

B

Figure C.8: WVR interface Xilinx schematic
U2 VCC U16 PORST 0 INV U1 GND
Drawn: Date:

U12 1

3_6864MHZ

0

CE C CLR

Q0 Q1 Q2 Q3 CEO TC

CB4CE

ATNF RECEIVER GROUP
Checked: Approved:

A

Power on Reset

Error : csiro.bmp file not found.
Originator:

WVR Xilinx
A

Dataset Comms & ADC
XILINX PARTTYPE=XCS20XLTQ144-4
Issued: Schematic Filename:

K:\wvrxil\comms.sch
Assembly Drawing No.: Revision: Sheet: Total:

2
2 3 4

7

APPENDIX C: WVR Interface Schematics

1


App endix D Conversion Interface Schematics

1

2

3

4

ADC 1.sch
D

Xilinx 1.sch
D

Connector.sch

Power Supply.sch

Digital IO 1.sch

C

C

B

B

Drawn:

Date:

ATNF RECEIVER GROUP
Error : csiro.bmp file not found.

Checked:

Approved:

MM Conversion Interface Boa
A

A
Originator:

Project Sheet
Schematic Filename:

Issued:

K:\MMConversionInterface\Conversion main.prj
Revision: Sheet: Total:

Assembly Drawing No.:

1.0
1 2 3 4

1

6

Figure D.1: MM conversion interface pro ject sheet

105


106

1 4

2

3

+15V
14 3

-15V

U9
V+ VSS-

MAX309CSE
D 9 8

D B OUT A OUT

7

A0 A1 EN 1A 2A 3A 4A 1B 2B 3B 4B +15V
GND

ANA0 ANA1 ANEN1 AN1+ AN2+ AN3+ AN4+ AN1AN2AN3AN41 16 2 4 5 6 7 13 12 11 10 IN IN IN IN IN IN IN IN

U17 SSM-2143
VCC

15

L2 100uH

+5V

2 -IN Sense

V+

5

R2
VCC +15V Vo 6

+5V

R7 1M R1 200R 1%
1

33K2 1%

U2

+
14 3

C -15V 3 +IN
V-

C19 4n7 C2 2u2 C3 2u2

C

U10
V+ VSS-

MAX309CSE

REF

C20 10uF

C21 10uF

B OUT A OUT -15V

9 8

4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 VIN AGND1 REF CAP AGND2 D15(MSB) D14 D13 D12 D11 D10 D9 D8 DGND VDIG VANA BUSY CS R/C BYTE D0 D1 D2 D3 D4 D5 D6 D7

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AnBSY AnEN AnST HIGH D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 EN 1A 2A 3A 4A 1B 2B 3B 4B IN IN IN IN IN IN IN IN
GND

ANA0 ANA1 ANEN2 AN5+ AN6+ AN7+ AN8+ AN5AN6AN7AN81 16 2 4 5 6 7 13 12 11 10

LTC1605-2CG

-15V
15

+15V

B

C11 100n
+15V

C12 100n

B

14 3

-15V

U11
V+ VSS-

A0 A1 EN 1A 2A 3A 4A 1B 2B 3B 4B B OUT A OUT 9 8 IN IN IN IN IN IN IN IN
GND

15

Figure D.2: MM conversion interface ADC schematic
MAX309CSE
Drawn: Date: Checked:

ATNF RECEIVER GROUP
Approved:

A

ANA0 ANA1 ANEN3 AN9+ AN10+ AN11+ AN12+ AN9AN10AN11AN121 16 2 4 5 6 7 13 12 11 10

Error : csiro.bmp file not found.
Originator:

MM Conversion Interface Boa
A

ADC
Issued: Schematic Filename:

K:\MMConversionInterface\ADC.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

3

6

APPENDIX D: Conversion Interface Schematics

1


1 4

2

3

P1A AN1+ DIG1/2 DIG5/2 SMPL34F J3P DIG3/5 SMPL34F J3C AN8+
+3V3

J2A DIG3/0 AN7+ SMPL34F J2^ DIG3/1 AN7SMPL34F J2_
+3V3

J2O DIG3/4 SMPL34F J3B

J2]

J3A

J3O

J3]

A

+20V

SMPL20M P1B AN1DIG1/3 SMPL34F J2C AN2+ DIG1/4 SMPL34F J2D AN2DIG1/5
+3V3

SMPL34F J2B

SMPL34F J2P

SMPL34F J3^
D

D

B

SMPL20M P1C DIG3/6 SMPL34F J3D AN8SMPL34F J2a AN9+ SMPL34F J2T DIG1/7 SMPL34F J2G AN4+ DIG2/0 SMPL34F J2H AN4DIG2/1 SMPL34F J2I AN5+ DIG2/2 SMPL34F J2J AN5DIG2/3 SMPL34F J2K AN6+ DIG2/4 SMPL34F J2L AN6DIG2/5 SMPL34F J2M DIG1/0 SMPL34F J2N DIG1/1 SMPL34F SMPL34F DIG2/7 SMPL34F J2\ DIG3/3 SMPL34F
Drawn: Date:

SMPL34F J2Q

SMPL34F J3Q

SMPL34F J3_

C

-20V

SMPL20M P1D DIG3/7 SMPL34F J3E DIG4/0 SMPL34F J3F AN9SMPL34F J2U AN10+ SMPL34F J2V AN10SMPL34F J2W AN11+ SMPL34F J2X AN11SMPL34F J2Y AN12+ SMPL34F J2Z AN12SMPL34F J2[ DIG2/6 DIG3/2 SMPL34F J3N DIG5/1 SMPL34F SMPL34F J3M DIG5/0 SMPL34F J3\ SMPL34F J3L DIG4/7 SMPL34F J3[ SMPL34F J3K DIG4/6 SMPL34F J3Z SMPL34F J3J DIG4/5 SMPL34F J3Y SMPL34F J3I DIG4/4 SMPL34F J3X SMPL34F J3H DIG4/3 SMPL34F J3W SMPL34F SMPL34F J3G DIG4/2 SMPL34F J3V DIG4/1 SMPL34F J3U SMPL34F J3T SMPL34F J3S
+3V3

SMPL34F J2R

SMPL34F J2`

SMPL34F J3R

SMPL34F J3`

D

+9V

SMPL20M P1E AN3+ DIG1/6 SMPL34F J2F AN3SMPL34F J2b

SMPL34F J2E

SMPL34F J2S

SMPL34F J3a

E

TXD+

SMPL20M P1F

SMPL34F J3b

F

TXD-

C

SMPL20M P1G

SMPL34F
C

H

RXD+

SMPL20M P1H

J

RXD-

SMPL20M P1I

K

EVENT+

APPENDIX D: Conversion Interface Schematics

SMPL20M P1J

L

EVENT-

SMPL20M P1K

M

WAVE+

B

SMPL20M P1L

B

N

WAVE-

SMPL20M P1M

P

BDIG3/6

SMPL20M P1N

R

BDIG3/7

SMPL20M P1O

Figure D.3: MM conversion interface connector schematic
Checked: Approved:

S

BDIG6/6

SMPL20M P1P

ATNF RECEIVER GROUP
Error : csiro.bmp file not found.
Originator:

T

BDIG6/7

MM Conversion Interface Boa
A

A

SMPL20M

Connectors
Issued: Schematic Filename:

K:\MMConversionInterface\Connector.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

3

6

107

1


108

1 4

2

3

D

D

U5
VCC

U8 C9
VCC VCC B A GND 5 6 DE DI GND 5 A 3 6 7 RE B 8 R0 7 VCC

RXD
1 R0 RE DE DI 2 3 4 1 2 8

EVENT 100n RXDEVENT+ EVENT-

C 4

R10 120R R8 R9 1K 1K RXD+
VCC

C

MAX487 U6 C10
1 R0 RE DE DI GND 5 DI 4 A 6 DE B 7 RE VCC R0 B A GND VCC 2 3 4 8 VCC

MAX487 U7
VCC

WAVE
1 2 3

8 7 6 5

VCC

100n TXDTXD+

WAVEWAVE+

TXDEN TXD MAX487 MAX487

B

B

Figure D.4: MM conversion interface digital I/O schematic
Drawn: Date:

ATNF RECEIVER GROUP
Checked: Approved:

Error : csiro.bmp file not found.
Originator:

MM Conversion Interface Boa
A

A

Digital I/O
Issued: Schematic Filename:

K:\MMConversionInterface\Digital 1.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

4

6

APPENDIX D: Conversion Interface Schematics

1


1 4

2

3

+3V3

12 25 37 51 63 75 89 100

D
VCC VCC VCC VCC VCC VCC VCC VCC

U?

D

+3V3

RP1 SEREN PROG DIN INIT 4K7
+3V3 VCC
8

J1 U4

D1 D2 D3 D4 D5 D6 D7 DIG1/0 DIG1/1 DIG1/2 DIG1/3 DIG1/4 DIG1/5 DIG1/6 DIG1/7 DIG2/0 DIG2/1 DIG2/2 3.6864MHz

C SEREN

VCC

7

DIN CCLK SEREN BAS216 D1 HEADER 5
1 2 3 4 5

GND

CCLK DIN DONE INIT
2 1 4 3 D CE RST CEO 6

C

AT17LV256
5

APPENDIX D: Conversion Interface Schematics

PROG

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK6-I/O TDO-O I/O GCLK7-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK8-I/O

58 59 60 61 62 65 66 67 68 69 70 71 73 76 78 79 80 81 82 83 84 85 86 87 90 91 92 93 94 95 96 97 98 99

B +3V3 +3V3

DIG2/3 DIG2/4 DIG2/5 DIG2/6 DIG2/7 DIG3/0 DIG3/1 DIG3/2 DIG3/3 DIG3/4 DIG3/5 DIG3/6 DIG3/7 DIG4/0 DIG4/1 DIG4/2 DIG4/3 DIG4/4 DIG4/5 DIG4/6 DIG4/7 DIG5/0 DIG5/1 DIG5/2 TXD RXD TXDEN WAVE EVENT ANEN1 ANEN2 ANEN3 ANA0 ANA1 AnBSY AnEN AnST HIGH D0 INIT DONE PROG DIN CCLK
GND GND GND GND GND GND GND GND

B

C8
8

2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 27 28 29 30 31 32 33 34 35 39 40 41 42 43 44 45 46 47 48 53 54 55 56 57 GCLK1-I/O I/O I/O/TDI I/O/TCK I/O/TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK2-I/O GCLK3-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK4-I/O I/O GCLK5-I/O I/O I/O I/O INIT-I/O DONE PROG DIN-I/O CCLK PWRDN M1 M0 36 50 52 72 74 26 22 24

+3V3

100n

V

1 EN
G

OUT

5

3.6864MHz

4

Figure D.5: MM conversion interface Xilinx schematic
U13 3.6864MHz
Drawn: Date:

1 11 23 38 49 64 77 88

C13 100n

C14 100n

C15 100n

C16 100n

XCS20XLVQ100

ATNF RECEIVER GROUP
Checked: Approved:

Error : csiro.bmp file not found.
Originator:

MM Conversion Interface Boa
A

A

Xilinx
Issued: Schematic Filename:

K:\MMConversionInterface\Xilinx 1.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

5

6

109

1


110

1 4

2

3

D

D

+9V +15V 1 VIN VOUT 3 5

VCC

+20V 8 IN OUT

U? LM78L15ACM U12 ZLD0500 C6 10p C4 2u2 C24 4u7 35V
GND GND GND GND

C18 100n
SPG 8 SC
GND

C25 22u 16V
4 LBF 1

C17 100n

C

2 3 6 7

C

C23 4u7 35V
5

VCC
GND

7

U1 ZLD0330
+3V3 5 3 VIN VOUT

7 6 3 2

C22 100n
1 -15V
GND

IN IN IN IN OUT

-20V

U? LM79L15ACM
4 SC LBF 1

C7 100n
SPG 8

C5 10p

C1 2u2

B

7

B

Figure D.6: MM conversion interface power supply schematic
Drawn: Date:

ATNF RECEIVER GROUP
Checked: Approved:

Error : csiro.bmp file not found.
Originator:

MM Conversion Interface Boa
A

A

Power Supply
Issued: Schematic Filename:

K:\MMConversionInterface\Power Supply.sch
Assembly Drawing No.: Revision: Sheet: Total:

1.0
2 3 4

6

6

APPENDIX D: Conversion Interface Schematics

1


App endix E LO Interface Schematics

111


112

1 8

2

3

4

5

6

7

+20V 8 IN
GND GND GND GND GND GND GND GND

U9 LM78L15ACM
+15V 1 IN OUT 8 1 +9V VCC OUT

U8 LM78L05ACM

J2 C23 4u7 35V C17 100n
2 3 6 7

Y11
D

C24 22u 16V

C16 100n

C4 2u2

Y10
2 3 6 7

D

Y9 KILL_L86 Y8
VCC

C7
+3V3
5 8

Y7 C22 4u7 35V
+9V
V

Y6 U1 ZLD0330
+3V3 5 3 VIN VOUT

100n RP1 3.6864MHz
+3V3 VCC
8

Y5
GND

7 6 3 2 IN IN IN IN OUT 1 SPG

Y4 YIG_STB Y3 C6 100n
8

C5 10p C1 2u2 U11 3.6864MHz J1 DIN CCLK SEREN BAS216 D1 HEADER 5
1 2 3 4 5
4 G

C18 100n CLKEN
1 EN OUT 5

SEREN PROG DIN INIT 4K7 U13
SEREN 7

DB25/M
+15V
5 3 13

GND

1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
7

Y2 LOCK Y1 SBSEL Y0 CCLK DIN DONE INIT
2 1 4 3 D CE RST CEO 6
VCC

SC

GND

-20V 4 LBF 1

U10 LM79L15ACM
-15V

AT17LV256 PROG
+3V3

-15V +15V VCC

U6
VV+ 7 8

L1 4.7uH

+5V

C

12 25 37 51 63 75 89 100

ANEN1 ANA0 ANA1 ANA2 U14
VCC +5V 2 6 COM 8 3

R2 R1 200R 1% 33K2 1% U2

C

U12
VCC VCC VCC VCC VCC VCC VCC VCC

OP-177
4 1

C19 4n7 C2 2u2 C3 2u2 C20 10uF C21 10uF

EN A0 A1 A2 NO NO NO NO NO NO NO NO 1 2 3 4 5 6 7 8
GND

DET_BIAS I_COIL REF_DET IF_DET V_DRIVE SPARE_1 SPARE_2 SPARE_3
-15V

2 1 16 15 4 5 6 7 12 11 10 9

MAX308CSE
14

-15V

+15V

P1A C10 100n LTC1605-2CG
+15V

P1K C11 100n

A

+20V

M

SPARE4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 VIN AGND1 REF CAP AGND2 D15(MSB) D14 D13 D12 D11 D10 D9 D8 DGND VDIG VANA BUSY CS R/C BYTE D0 D1 D2 D3 D4 D5 D6 D7

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AnBSY AnEN AnST HIGH D0 D1 D2 D3 D4 D5 D6 D7

SMPL20M P1B JP1
-15V
3 13

SMPL20M P1L

B

N

ANEN1 ANEN2 ANEN3 ANA0 ANA1 ANA2 AnBSY AnEN AnST HIGH D0 D1 D2 D3 D4 D5 D6 D7

SMPL20M P1C U7
VV+

SMPL20M P1M
1 3 5 7 9

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 YIG_STB KILL_L86 LOCK SBSEL DIGSP1 DIGSP2 DIGSP3 DIGSP4
2 4 6 8 10

C

-20V

P

SPARE5

SMPL20M P1D

SMPL20M P1N

D 8 +3V3

+9V COM

R

HEADER 5X2

B

B

SMPL20M P1E RP2 U3
VCC

SMPL20M P1O

ANEN2 ANA0 ANA1 ANA2 SPARE4 SPARE5 SPARE6 C8

E

TXD+ RXD
1 R0 RE DE DI GND 5 A 6 B 7 VCC 2 8

S

SPARE6

D2 LED D3 LED

SMPL20M P1F
GND

SMPL20M P1P 100n RXD-

F

TXDMAX308CSE
14

T

2 1 16 15 4 5 6 7 12 11 10 9 EN A0 A1 A2 NO NO NO NO NO NO NO NO 1 2 3 4 5 6 7 8

SMPL20M P1G
3 4

SMPL20M P1Q

220R R5 120R R3 R4 1K 1K RXD+
VCC

D4 LED D5 LED

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK6-I/O TDO-O I/O GCLK7-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK8-I/O

58 59 60 61 62 65 66 67 68 69 70 71 73 76 78 79 80 81 82 83 84 85 86 87 90 91 92 93 94 95 96 97 98 99

H

RXD+

U

DIGSP1

SMPL20M P1H MAX487 U5
VCC

SMPL20M P1R

INIT DONE PROG DIN CCLK
+3V3
GND GND GND GND GND GND GND GND

J

RXDU4 C9
1 7 6

V

DIGSP2 EVENT
1 R0 RE DE A B VCC 2 3 8 VCC

2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 27 28 29 30 31 32 33 34 35 39 40 41 42 43 44 45 46 47 3.6864MHz 48 CLKEN 53 TXD 54 RXD 55 TXDEN 56 EVENT 57

SMPL20M P1J EVENT+ TXDEN
3 DE DI GND A 4 5 6 5 VCC 2 RE B 7 4 DI GND

SMPL20M P1T

100n

TXDTXD+ C12 100n C13 100n C14 100n C15 100n

L

EVENTTXD MAX487

X

DIGSP4

SMPL20M MAX487

SMPL20M

A

Drawn:

Date:

1 11 23 38 49 64 77 88

Figure E.1: MM local oscillator interface schematic
GCLK1-I/O I/O I/O/TDI I/O/TCK I/O/TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK2-I/O GCLK3-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK4-I/O I/O GCLK5-I/O I/O I/O I/O INIT-I/O DONE PROG DIN-I/O CCLK PW RDN M1 M0 +3V3 36 50 52 72 74 26 22 24

SMPL20M P1I EVENTR0 VCC 8

SMPL20M P1S

K

EVENT+

W

DIGSP3

XCS20XLVQ100

ATNF RECEIVER GROUP
Checked: Approved:

A

Error : csiro.bmp file not found.
Originator:

MM LO Interface Board
Issued: Schematic Filename:

K:\MMConversionInterface\MM LO Interface.sch
Assembly Drawing No.: Revision: Sheet: Total:

B
2 3 4 5 6 7

1
8

1

APPENDIX E: LO Interface Schematics

1


1 8

2

3

4

5

6

7

P32 U? INV U?
O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

U? LED1 LED2 LED3
E I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

P58 OPAD P59 OPAD P60
D

U? U? BUFE16

15Hz

BRXD
I3 I2 I1 I0 O3 O2 O1 O0

CE C CLR

Q0 Q1 CEO TC

OPAD P33 OPAD P34 OPAD P35 LED4 U? U? YIGRD OPAD

INV OBUF4

CB2CE

D

U? U? INV

OPAD P61 OPAD P62 OPAD P65 OPAD P66 OPAD P67 OPAD P68 OPAD P69 OBUF16 OPAD P70 OPAD P71

15Hz STB U? U? 16KHz 15Hz U? A4 A5 A6 A7
A0 A1 A2 A3 0 1 2 3 4 5

CE C CLR

Q0 Q1 CEO TC

CB2CE

U? U? INV STB INV WCK
CE C CLR Q0 Q1 CEO TC F8M F500K F16K F490 F15

15Hz PAR OSC4

CB2CE

U?
CE C CLR Q0 Q1 CEO TC

Clock Divider
U? INV

15Hz ERR YIGEN WCK 0
CE C CLR

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D1 D1 D1 D1 D1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

CB2CE

0-15 16-31 32-47 48-63 64-95 96-111 112-127 128-143

P55 FD16CE U? YIGEN WCK U17
RXD TXD TXD_EN

U?

Status LED Drivers

DIF2

C

IPAD A8
E

P54 D4_16E U? A8 ANEN WR WR STB AND2B2 U? ANEN STB

IBUF U?

BRXD

U?

OPAD P73 OBUF AND2 P14 IPAD P15 D0 OPAD

C

DIF1

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

OPAD

P56

OBUF U?

TXD_EN

DIFDIR1 PAR ERR
PAR ERR WR STB

OPAD

OBUF

APPENDIX E: LO Interface Schematics

ADD< ADD< ADD< ADD< ADD< ADD< ADD< ADD< ADD<

0 1 2 3 4 5 6 7 8

> > > > > > > > >

A0 A1 A2 A3 A4 A5 A6 A7 A8 U?

U?
ADCRQ STB

D1 IPAD P16 IPAD P17 IPAD P18 IBUF8
ADCEN ANST ANHIGH BUSY

P48
CLK

U?

D2 D3 D4 IPAD P19 U? IPAD P20 OBUF IPAD P21 D5 D6 D7

CLK

3_6864MHZ

IPAD
A0 A1 A2 A3

P53

BUFG U?

1

A0 A1 A2 A3

ADCDATA< ADCDATA< ADCDATA< ADCDATA< ADCDATA< ADCDATA< ADCDATA< ADCDATA<

0 1 2 3 4 5 6 7

> > > > > > > >

O0 O1 O2 O3 O4 O5 O6 O7

I0 I1 I2 I3 I4 I5 I6 I7

OPAD

OBUF

DSA = 4
1 1 0 1
BAUD< BAUD< BAUD< BAUD< 0 1 2 3 > > > >

0 0 1 0 0
DSA< DSA< DSA< DSA< DSA< 0 1 2 3 4 > > > > >

38400 BPS
U? 0-15 WR DATASET D4_16E AND2B1 U? AND2 U?
E

B

U? A3 U? P3 OBUF U? OPAD

0
RST

DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15> D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 YIGRD Read1 Read2 Read3 Read4 Read5 Read6 Read7 Read8 Read9 Read10 Read11 Read12 Read13 Read14 Read15

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3_6864MHZ PORST

DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8> DATA<9> DATA<10> DATA<11> DATA<12> DATA<13> DATA<14> DATA<15> CLK RST

U?

B

IPAD P9 OBUF ADCRD16 P2 OBUF U? A3 AND2B1 A0 OPAD P5 OBUF U? A1 OBUF U? A2 OBUF OPAD P6 OPAD P7 OPAD U? OPAD P10 OPAD P13 OBUF U8 OPAD P8 IBUF IPAD

AnEN AnST HIGH AnBSY

Dataset State Machine
A0 A1 A2 A3
A0 A1 A2 A3

U? A4 A5 A6 A7 ANEN AND5B4

U? 1 VCC U? 0 GND 0-15 WR AND2
E

ADC Sequencing

Figure E.2: MM local oscillator interface Xilinx schematic
XILINX PARTTYPE=XCS20XLVQ100-4
D4_16E U?
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

YIGEN Write1 Write2 Write3 Write4 Write5 Write6 Write7 Write8 Write9 Write10 Write11 Write12 Write13 Write14 Write15

Address Decoder

A

Drawn:

Date:

ATNF RECEIVER GROUP
Checked: Approved:

A

Originator:

Interface Comms
Issued: Schematic Filename:

K:\MMConversionInterface\xilinx.sch
Assembly Drawing No.: Revision: Sheet: Total:

1
2 3 4 5 6 7 8

1

113

1


114

APPENDIX E: LO Interface Schematics


App endix F Fibre Mux Schematics

115


116

APPENDIX F: Fibre Mux Schematics

1

2

3

4

H

H

G

G

VCC

R2 10K
VCC 1 3 2 4

U4

VCC

C3 100n HFD3023

VCC 1 3 4 2

U8
F

F

R8 180R
+9V 1

HFE4074 U5
1 3 2 4

U12 LM7805
Vin Vout 3

VCC

Q4 BC848
VCC VCC

GND

C8 10u 16V

C7 10u 16V

R6 10K

C4 100n HFD3023

2

VCC 1 3 4 2

U9

R9
E

180R Q3 BC848
VCC VCC

E

HFE4074 U6
1 3 2 4

VCC

R3 10K
VCC

R5 10K

C5 100n HFD3023

U3 C6 100n HFD3023
1 3 2 4

VCC

U11B
4 6 5 VCC 1 3 4 2

U10

DM74LS00

R4 10K Q2 BC848

R10 180R

HFE4074 U1
VCC 1 2 R0 RE DE DI VCC B A GND 8 7 6 5 D

D

U7
1 3 4 2

VCC

C1 100n TXD+ TXD+9V

VCC

3 4

HFE4074 R7 180R Q1 R1 10K BC848
C 3 1 1 2 3 4

J1
1 2 3 4 5 6

MAX487 U11A
2

U2
R0 RE DE DI VCC B A GND 8 7 6 5

VCC

C2 100n RXD+ RXD-

CON6
C

DM74LS00

MAX487

B

B

Drawn:

Date:

ATNF RECEIVER GROUP
Error : csiro.bmp file not found.
A

Checked:

Approved:

A
Originator:

Dataset Fibre Mux
Schematic Filename:

Issued:

K:\Fibre Modems\fibre mux.sch
Revision: Sheet: Total:

Assembly Drawing No.:

1.0
1 2 3 4

1

1

Figure F.1: MM fibre mux schematic


App endix G Labwindows/CVI Source Co de
G.1
G.1.1

Dataset Test Panel
dataset serv.c

/***************************************************************************/ /* */ /* Labwindows Dataset Bus TCP/IP Server. */ /* */ /* Revision 0.1 by Suzy Jackson */ /* */ /* Allows computers to access a dataset bus using TCP/IP. */ /* */ /* Protocol is: command dataset.address [data] */ /* command is either "set" or "show" */ /* dataset is an ascii string containing the dataset name */ /* (eg "c13_ds") */ /* address is an ascii integer containing the register address */ /* data is an ascii integer containing data to be loaded. */ /* */ /* The server responds with either */ /* command dataset.address [data] */ /* or */ /* command dataset address [data] returned error */ /* where error is the error number returned by the relevant */ /* dataset comms routine. */ /* */ /***************************************************************************/ #include #include #include #include #include #include #include #include /* Needed if linking in external compiler */ "dset_96.h" /* Dataset serial comms routines */ "dataset_server.h"

117


118

APPENDIX G: Labwindows/CVI Source Code

#define CONTROL 0xC0000000 #define MONITOR 0x40000000 #define #define #define #define #define #define #define #define #define #define #define #define #define #define ESC SYN NAK ACK BEL 0x1b 0x16 0x15 0x06 0x07 */

PARITY 1 /* odd DATA_BITS 8 STOP_BITS 1 IN_QUEUE_SIZE 64 OUT_QUEUE_SIZE 64 MSGHD 71 CONTROL 0xC0000000 MONITOR 0x40000000 ACK 0x06

struct loboss_msg { char msgHD; unsigned char msglen; char msg[256]; }; int port, port_open, panelHandle, TCPHandle; void int_to_bytes(int num, char *byte) { short i; for (i=0;i<=3;i++) { byte[i]=num; num=(num >> 8); } }

unsigned int bytes_to_int(char *byte, int num_bytes) { short i; unsigned int num = byte[0]; unsigned char ch; for (i=1;i

APPENDIX G: Labwindows/CVI Source Code
} return(num); } int Initialise_Dataset(int ds_address, int port, int baud) { /* Error codes: 0 success -1 comms error */ int data; extern int port_open; if (!port_open) { if (OpenComConfig (port, "", baud, PARITY, DATA_BITS, STOP_BITS, IN_QUEUE_SIZE, OUT_QUEUE_SIZE)) return(-1); port_open=1; } FlushOutQ (port); FlushInQ (port); SetComTime (port, 0.5); return(0); } void Close_All_Datasets(port) { CloseCom(port); } int ReadResponse(int* response) /* TESTED OK */ { extern int port; char read_buff[3], flag, txferstring[40]; ComRd (port, &flag, 1); if (rs232err) { SetCtrlVal (panelHandle, PANEL_HISTORY, GetRS232ErrorString (rs232err)); SetCtrlVal (panelHandle, PANEL_HISTORY, " "); return(-1); } sprintf (txferstring, "%X ", flag&0xff); SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); ComRd (port, read_buff, 2); sprintf (txferstring, "%X %X ", read_buff[0]&0xff, read_buff[1]&0xff); SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); if (flag == ACK || flag == BEL) { if (read_buff[0] == ESC) { Decode(read_buff); ComRd(port, &read_buff[1],1); sprintf (txferstring, "%X ", read_buff[1]&0xff);

119


120

APPENDIX G: Labwindows/CVI Source Code

SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); } if (read_buff[1] == ESC) { ComRd(port, &read_buff[2], 1); sprintf (txferstring, "%X ", read_buff[2]&0xff); SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); Decode(&read_buff[1]); } *response = bytes_to_int(read_buff, 2); while (GetInQLen (port) >0) { ComRd (port, read_buff, 1); sprintf (txferstring, "%X ", read_buff[0]&0xff); SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); } return(0); } else { while (GetInQLen (port) >0) { ComRd (port, read_buff, 1); sprintf (txferstring, "%X ", read_buff[0]); SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); } return (-2); } } void Decode(char* esc_seq) { switch (esc_seq[1]) { case '0': esc_seq[0] = ESC; break; case '1': esc_seq[0] = SYN; break; case '2': esc_seq[0] = ACK; break; case '3': esc_seq[0] = BEL; break; case '4': esc_seq[0] = NAK; break; default: break; } } int SendMessage(int message) /* TESTED OK */

/* TESTED OK */


APPENDIX G: Labwindows/CVI Source Code
{ extern int port; char write_buff[10], byte[4], current; int index = 0, count = 3; write_buff[index++] = SYN; int_to_bytes(message, byte); while(index < 10) { if (count >= 0) { switch (current = byte[count--]) { case ESC: write_buff[index++] = ESC; write_buff[index++] = '0'; break; case SYN: write_buff[index++] = ESC; write_buff[index++] = '1'; break; default: write_buff[index++] = current; break; } } else write_buff[index++] = NULL; } if (ComWrt(port, write_buff, 10) != 10) return(-1); else return(0); } int Dataset_Out(int ds_address, int control_point, int data_out) { /* Error codes: 0 -1 -2 -3 -4 success comms error dataset error invalid control point invalid data out

121

*/ int message, err; char reply[3], txferstring[40]; if (control_point < 0 || control_point > 511) return(-3); if (data_out < 0 || data_out > 0xffff) return(-4); message = CONTROL + (ds_address << 25) + (control_point << 16) + data_out; if (err = SendMessage(message)) return(err); ComRd(port, reply, 3); if (rs232err) { SetCtrlVal (panelHandle, PANEL_HISTORY,


122

APPENDIX G: Labwindows/CVI Source Code

GetRS232ErrorString (rs232err)); SetCtrlVal (panelHandle, PANEL_HISTORY, " "); } else { sprintf (txferstring, "%X %X %X ", reply[0]&0xff, reply[1]&0xff, reply[2]&0xff); SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); } while (GetInQLen (port) >0) { ComRd (port, reply, 1); sprintf (txferstring, "%X ", reply[0]&0xff); SetCtrlVal (panelHandle, PANEL_HISTORY, txferstring); } if (reply[0] != ACK) return(-2); else return(0); } int Dataset_In(int ds_address, int monitor_point, int *data_in) { /* Error codes: 0 -1 -2 -3 success comms error dataset error invalid control point

*/ int message, err, response; if (monitor_point < 0 || monitor_point > 511) return(-3); message = MONITOR + (ds_address << 25) + (monitor_point << 16); if (err = SendMessage(message)) return(err); if (err = ReadResponse(&response)) return(err); *data_in = (response & 0xffff); return(0); }

int dsetlookup (char *dataset) /* Provides a quick conversion from dataset name to dataset number. */ { if (!strcmp (dataset, "c11_ds")) if (!strcmp (dataset, "c13_ds")) if (!strcmp (dataset, "c31_ds")) if (!strcmp (dataset, "c41_ds")) /* we don't understand the name, return atoi(dataset); } return 10; return 16; return 17; return 18; so let's assume it's a decimal */

int CVICALLBACK TCPServerCallback (unsigned handle, int event, int error, void *callbackData)


APPENDIX G: Labwindows/CVI Source Code
{ char command [12], dataset [12], reqstring [256]; char *temp; int err = 0, dataSize = 256, address, data; struct loboss_msg buffer; TCPHandle = handle; switch (event) { case TCP_CONNECT: TCPHandle = handle; SetCtrlVal (panelHandle, PANEL_HISTORY, "New connection established\n"); break; case TCP_DATAREADY: if ((dataSize = ServerTCPRead(TCPHandle, &buffer, dataSize, 1000)) == -kTCP_ConnectionClosed) { SetCtrlVal (panelHandle, PANEL_HISTORY, "TCP Read Error - connection closed\n"); } if (buffer.msglen>2) { /* extract the message from the buffer */ memcpy (reqstring, &buffer.msg, buffer.msglen-2); /* append a NULL so that it looks like a string */ reqstring [buffer.msglen-2]=0; /* remove the . between the dataset name and register address */ if (temp=strchr(reqstring,'.')) *temp = ' '; /* suck out the gist of the message */ sscanf (reqstring,"%s %s %d %d", command, dataset, &address, &data); if (!strcmp (command,"show")) { if (err = Dataset_In (dsetlookup (dataset), address, &data)) { sprintf (buffer.msg, " show %s.%d returned %d\n", dataset, address, err); } else { sprintf (buffer.msg, " show %s.%d %d", dataset, address, data); } } else if (!strcmp (command, "set")) { if (err = Dataset_Out (dsetlookup (dataset), address, data)) { sprintf (buffer.msg, " set %s.%d %d returned %d", dataset, address, data, err); } else { sprintf (buffer.msg, " set %s.%d %d", dataset, address, data); } } else { sprintf (buffer.msg, " %s is not a valid message", reqstring); err = -1;

123


124

APPENDIX G: Labwindows/CVI Source Code
} buffer.msglen = strlen (buffer.msg) + 2; buffer.msgHD = MSGHD; SetCtrlVal (panelHandle, PANEL_HISTORY, &buffer.msg); SetCtrlVal (panelHandle, PANEL_HISTORY, "\n"); if (ServerTCPWrite (TCPHandle, &buffer, buffer.msglen, 1000)<0) { SetCtrlVal (panelHandle, PANEL_HISTORY, "TCP Write Error - connection closed\n"); }

} sprintf (buffer.msg, " %d",err); buffer.msglen = strlen (buffer.msg) + 2; buffer.msgHD = MSGHD; if (ServerTCPWrite (TCPHandle, &buffer, buffer.msglen, 1000)<0) { SetCtrlVal (panelHandle, PANEL_HISTORY, "TCP Write Error - connection closed\n"); } break; case TCP_DISCONNECT: SetCtrlVal (panelHandle, PANEL_HISTORY, "Connection closed by client\n"); break; } return (0); }

int main (int argc, char *argv[]) { char miscstring [11]; int errval; if (InitCVIRTE (0, argv, 0) == 0) return -1; /* out of memory */ if ((panelHandle = LoadPanel (0, "dataset_server.uir", PANEL)) < 0) return -1; DisplayPanel (panelHandle); RunUserInterface (); return 0; }

int CVICALLBACK Shutdown (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: QuitUserInterface (0); break; } return 0; }


APPENDIX G: Labwindows/CVI Source Code

125

void CVICALLBACK Menu (int menuBar, int menuItem, void *callbackData, int panel) { int err; char errstring [80], hoststring [256], miscstring [11]; switch (menuItem) { case MENU_FILE_QUIT: QuitUserInterface (0); break; case MENU_SETUP_COM1: case MENU_SETUP_COM2: SetMenuBarAttribute (menuBar, MENU_SETUP_COM1, ATTR_CHECKED, 0); SetMenuBarAttribute (menuBar, MENU_SETUP_COM2, ATTR_CHECKED, 0); SetMenuBarAttribute (menuBar, menuItem, ATTR_CHECKED, 1); if (menuItem == MENU_SETUP_COM1) port = 1; else port = 2; PromptPopup ("Enter Baudrate", "Please type the baudrate being used by the datasets.\n (generally either 4800 or 38400)", miscstring, 10); if ((err = Initialise_Dataset(0, port, atoi(miscstring)))== -1) { /* Note we don't care if the dataset doesn't respond */ SetCtrlVal (panelHandle, PANEL_HISTORY, "Unable to open com port.\n"); SetMenuBarAttribute (menuBar, menuItem, ATTR_CHECKED, 0); } break; case MENU_SETUP_TCP: PromptPopup ("Enter Port Number", "Please enter the port number\n 0 for no TCP", miscstring, 10); SetWaitCursor (1); if (atoi(miscstring)) { SetCtrlVal (panelHandle, PANEL_HISTORY, "Registering server: "); if (RegisterTCPServer(atoi(miscstring), TCPServerCallback, NULL)<0) { SetCtrlVal (panelHandle, PANEL_HISTORY, "Failed\n"); } else SetCtrlVal (panelHandle, PANEL_HISTORY, "Successful\n"); } SetWaitCursor (0); break; default: break; } } int CVICALLBACK send (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { int address, data, dataset, err; struct loboss_msg buffer;


126

APPENDIX G: Labwindows/CVI Source Code

switch (event) { case EVENT_COMMIT: GetCtrlVal (panelHandle, PANEL_dsa, &dataset); GetCtrlVal (panelHandle, PANEL_fa, &address); GetCtrlVal (panelHandle, PANEL_data, &data); if (err = Dataset_Out (dataset, address, data)) { sprintf (buffer.msg, " set %d.%d %d returned %d", dataset, address, data, err); } else { sprintf (buffer.msg, " set %d.%d %d", dataset, address, data); } SetCtrlVal (panelHandle, PANEL_HISTORY, &buffer.msg[0]); SetCtrlVal (panelHandle, PANEL_HISTORY, "\n"); break; } return 0; } int CVICALLBACK recv (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { int address, data, dataset, err; struct loboss_msg buffer; switch (event) { case EVENT_COMMIT: GetCtrlVal (panelHandle, PANEL_dsa, &dataset); GetCtrlVal (panelHandle, PANEL_fa, &address); if (err = Dataset_In (dataset, address, &data)) { sprintf (buffer.msg, " show %d.%d returned %d", dataset, address, err); } else { sprintf (buffer.msg, " show %d.%d %d", dataset, address, data); } SetCtrlVal (panelHandle, PANEL_data, data); SetCtrlVal (panelHandle, PANEL_HISTORY, &buffer.msg[0]); SetCtrlVal (panelHandle, PANEL_HISTORY, "\n"); break; } return 0; } int CVICALLBACK clear (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: FlushOutQ (port); FlushInQ (port); break; }


APPENDIX G: Labwindows/CVI Source Code
return 0; }

127

G.2
G.2.1

Receiver Monitor Panel
mm rx.c

/********************************************************************************/ /* CSIRO Australia Telescope */ /* Receiver Group */ /* */ /* Title: Millimetre Receiver Monitor Program V0.1 */ /* File: mm_rx.c */ /* Description: main routines. */ /* Author: Suzy Jackson */ /* Last Modified: 22-6-01 */ /********************************************************************************/

/********************************************************************************* Includes *********************************************************************************/ #include #include #include #include #include #include #include #include "panel.h" "Dset_96.h"

/* GUI defines */

#define CONTROL 0xC0000000 #define MONITOR 0x40000000 #define #define #define #define #define ESC SYN NAK ACK BEL 0x1b 0x16 0x15 0x06 0x07

int CVICALLBACK GetDataThread (void *functionData); /********************************************************************************* Global variables (not inc GUI ones) *********************************************************************************/ int port = 1, baud = 115200, port_open = 0; int panelHandle, aboutHandle, menuHandle; int MonitorGo = 1; /* useful info about the datasets */ /* Used to stop monitor process */


128

APPENDIX G: Labwindows/CVI Source Code

/********************************************************************************* Main Routine *********************************************************************************/ int main (int argc, char *argv[]) { if (InitCVIRTE (0, argv, 0) == 0) return -1; /* load all panels into memory */ if ((panelHandle = LoadPanel (0, "panel.uir", PANEL)) < 0) return -1; if ((aboutHandle = LoadPanel (0, "panel.uir", ABOUT)) < 0) return -1; if ((menuHandle = LoadMenuBar (panelHandle, "panel.uir", MENU)) < 0) return -1; /* insert the compile date in the about_date string */ #ifdef __STDC__ SetCtrlVal (aboutHandle, ABOUT_DATE, __DATE__); #endif /* display the introductory panel */ DisplayPanel (aboutHandle); /* open the port */ { if (OpenComConfig (port, "", baud, 1, 8, 1, 64, 64)) return(-1); port_open=1; } FlushOutQ (port); FlushInQ (port); /* start the data acquisition thread */ CmtScheduleThreadPoolFunction (DEFAULT_THREAD_POOL_HANDLE, GetDataThread, NULL, NULL); Delay (2.0); /* now hide the about screen and bring up the main panel */ HidePanel (aboutHandle); DisplayPanel (panelHandle); /* run the GUI, so people can control things. */ RunUserInterface (); } int Dataset_Out(int ds_address, int control_point, int data_out) { /* Error codes: 0 -1 -2 -3 -4 success comms error dataset error invalid control point invalid data out

*/ int message, err; char reply[3];


APPENDIX G: Labwindows/CVI Source Code
if (control_point < 0 || control_point > 511) return(-3); if (data_out < 0 || data_out > 0xffff) return(-4); message = CONTROL + (ds_address << 25) + (control_point << 16) + data_out; if (err = SendMessage(message)) return(err); ComRd(port, reply, 3); if (reply[0] != ACK) return(-2); else return(0); } int Dataset_In(int ds_address, int monitor_point, int *data_in) { /* Error codes: 0 -1 -2 -3 success comms error dataset error invalid control point

129

*/ int message, err, response; if (monitor_point < 0 || monitor_point > 511) return(-3); message = MONITOR + (ds_address << 25) + (monitor_point << 16); if (err = SendMessage(message)) return(err); if (err = ReadResponse(&response)) return(err); *data_in = (response & 0xffff); return(0); }

/********************************************************************************* GetDataThread Reads the analog monitor points, and displays the result on the panel meters. *********************************************************************************/ int CVICALLBACK GetDataThread (void *functionData) { int regdata, err, i, band; int dsplkup[48] = { PANEL_VDS_1A, PANEL_VGS_1A, PANEL_IDS_1A, PANEL_VDS_1B, PANEL_VGS_1B, PANEL_IDS_1B, PANEL_VDS_5A, PANEL_VGS_5A, PANEL_IDS_5A, PANEL_VDS_5B, PANEL_VGS_5B, PANEL_IDS_5B, int wlkup[48] = { 0, 1, 2, 3, 14, 15, 16, 17, PANEL_VDS_2A, PANEL_VDS_3A, PANEL_VGS_2A, PANEL_VGS_3A, PANEL_IDS_2A, PANEL_IDS_3A, PANEL_VDS_2B, PANEL_VDS_3B, PANEL_VGS_2B, PANEL_VGS_3B, PANEL_IDS_2B, PANEL_IDS_3B, PANEL_VDS_6A, PANEL_VDS_7A, PANEL_VGS_6A, PANEL_VGS_7A, PANEL_IDS_6A, PANEL_IDS_7A, PANEL_VDS_6B, PANEL_VDS_7B, PANEL_VGS_6B, PANEL_VGS_7B, PANEL_IDS_6B, PANEL_IDS_7B, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23, 24, PANEL_VDS_4A, PANEL_VGS_4A, PANEL_IDS_4A, PANEL_VDS_4B, PANEL_VGS_4B, PANEL_IDS_4B, PANEL_VDS_8A, PANEL_VGS_8A, PANEL_IDS_8A, PANEL_VDS_8B, PANEL_VGS_8B, PANEL_IDS_8B }; 11, 12, 13, 25, 26, 27,


130
28, 42, int klkup[24] = { 48, 62, int qlkup[24] = { 72, 86, 29, 43, 49, 63, 73, 87, 30, 44, 50, 64, 74, 88, 31, 45, 51, 65, 75, 89,

APPENDIX G: Labwindows/CVI Source Code
32, 46, 52, 66, 76, 90, 33, 34, 47 }; 53, 54, 67, 68, 77, 78, 91, 92, 35, 36, 37, 38, 39, 40, 41, 55, 69, 79, 93, 56, 70, 80, 94, 57, 58, 59, 60, 61, 71 }; 81, 82, 83, 84, 85, 95 };

int dewlkup[26] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121 }; int dewdlkup[26] = { PANEL_32V, PANEL_20V, PANEL__20V, PANEL_9V, PANEL_15R1, PANEL__15R1, PANEL_5R1, PANEL_15R2, PANEL__15R2, PANEL_5R2, PANEL_15R3, PANEL__15R3, PANEL_5R3, PANEL_15R4, PANEL__15R4, PANEL_5R4, PANEL_20K1, PANEL_70K1, PANEL_20K2, PANEL_70K2, PANEL_SUP1, PANEL_RET1, PANEL_SUP2, PANEL_RET2, PANEL_VAC1, PANEL_VAC2 }; for (;;) { GetCtrlVal (panelHandle, PANEL_MON_LNA, &band); switch (band) { case 0: for (i=0;i<24;i++) { if (MonitorGo) { Dataset_In (0, klkup[i], ®data); SetCtrlVal (panelHandle, dsplkup[i], ((double) (short) regdata)/8192); } } break; case 1: for (i=0;i<24;i++) { if (MonitorGo) { Dataset_In (0, qlkup[i], ®data); SetCtrlVal (panelHandle, dsplkup[i], ((double) (short) regdata)/8192); } } break; default: for (i=0;i<48;i++) { if (MonitorGo) { Dataset_In (0, wlkup[i], ®data); SetCtrlVal (panelHandle, dsplkup[i], ((double) (short) regdata)/8192); } } break; } for (i=0;i<26;i++) { if (MonitorGo) { Dataset_In (0, dewlkup[i], ®data); SetCtrlVal (panelHandle, dewdlkup[i],


APPENDIX G: Labwindows/CVI Source Code
((double) (short) regdata)/8192); } } if (MonitorGo) Dataset_In SetCtrlVal SetCtrlVal SetCtrlVal SetCtrlVal SetCtrlVal SetCtrlVal SetCtrlVal SetCtrlVal } } } { (1, 7, ®data); (panelHandle, PANEL_KA, (regdata&0x01)); (panelHandle, PANEL_KB, (regdata&0x02)); (panelHandle, PANEL_QA, (regdata&0x04)); (panelHandle, PANEL_QB, (regdata&0x08)); (panelHandle, PANEL_WA1, (regdata&0x10)); (panelHandle, PANEL_WA2, (regdata&0x20)); (panelHandle, PANEL_WB1, (regdata&0x40)); (panelHandle, PANEL_WB2, (regdata&0x80));

131

/********************************************************************************* Shutdown Called when the user hits the quit button. *********************************************************************************/ int CVICALLBACK Shutdown (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: QuitUserInterface (0); break; } return 0; }

/********************************************************************************* band_change Called when the user changes the displayed band. *********************************************************************************/ int CVICALLBACK band_change (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { int band, i; int lookup[24] = { PANEL_VDS_5A, PANEL_VGS_5A, PANEL_IDS_5A, PANEL_VDS_5B, PANEL_VGS_5B, PANEL_IDS_5B, PANEL_VDS_6A, PANEL_VGS_6A, PANEL_IDS_6A, PANEL_VDS_6B, PANEL_VGS_6B, PANEL_IDS_6B, PANEL_VDS_7A, PANEL_VGS_7A, PANEL_IDS_7A, PANEL_VDS_7B, PANEL_VGS_7B, PANEL_IDS_7B, PANEL_VDS_8A, PANEL_VGS_8A, PANEL_IDS_8A, PANEL_VDS_8B, PANEL_VGS_8B, PANEL_IDS_8B };


132

APPENDIX G: Labwindows/CVI Source Code

switch (event) { case EVENT_COMMIT: GetCtrlVal (panel, control, &band); for (i=0;i<24;i++) SetCtrlAttribute (panel, lookup[i], ATTR_DIMMED, (band!=2)); break; } return 0; }

/********************************************************************************* Menu Code to make sense of the pulldown menus. *********************************************************************************/ void CVICALLBACK Menu(int menubar, int menuItem, void *callbackData, int panel) { char about_string [200]; int temp; switch (menuItem) { case MENU_FILE_QUIT: QuitUserInterface(0); break; case MENU_HELP_ABOUT: DisplayPanel (aboutHandle); break; } }

/********************************************************************************* CLOSE_ABOUT Shuts down the about window. *********************************************************************************/ int CVICALLBACK CLOSE_ABOUT (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: HidePanel (aboutHandle); break; } return 0; }


APPENDIX G: Labwindows/CVI Source Code

133

/********************************************************************************* control Called when the user changes a control bit. *********************************************************************************/

int CVICALLBACK control (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: break; } return 0; }

G.3
G.3.1

Water Vap our Radiometer Server
wvr.c

/****************************************************************************/ /* CSIRO Australia Telescope */ /* Receiver Group */ /* */ /* Title: Water Vapour Radiometer Program V1.0 */ /* File: wvr.c */ /* Description: main routines. */ /* Author: Suzy Jackson */ /* Last Modified: 14-8-2000 */ /****************************************************************************/

/***************************************************************************** Includes *****************************************************************************/ #include #include #include #include #include #include #include #include #include #include #include "panel.h" "dset_96.h"


134

APPENDIX G: Labwindows/CVI Source Code

/***************************************************************************** Hardware Defines - these values need to reflect hardware reality *****************************************************************************/ #define MSGHD 71 #define MONITOR #define #define #define #define #define 0x40000000

DAQ_Device 1 DAQ_MAX 10 DAQ_MIN -10 Noise_Port "0" Noise_Line 0

#define DSA 2 #define PORT 1 #define BAUD 38400

/***************************************************************************** Structures *****************************************************************************/ /* a structure to store values we've read while we're waiting to write them to a file */ typedef struct List { double data[16]; char time[9]; double sec; struct List *next; } list; struct msg_type { char msgHD; unsigned char msglen; char msg[512]; }; /***************************************************************************** Prototypes *****************************************************************************/ list* Add_To_List (list *head, char *time, double sec, double *data); int Dataset_In(int ds_address, int monitor_point, int *data_in); int CVICALLBACK GetDataThread (void *functionData);

/***************************************************************************** Global variables


APPENDIX G: Labwindows/CVI Source Code
*****************************************************************************/ int port = PORT, port_open, panelHandle, menuHandle, aboutHandle, file_len = 99999999, list_len = 0; FILE *logfile; char logbase [MAX_PATHNAME_LEN] = {"wvr_data"}; char logpath [MAX_PATHNAME_LEN]; list *head = NULL; int TCPHandle, TCPConnect = 0, getdataflag = 0;

135

/***************************************************************************** TCPServerCallback Called when data is waiting on the TCP stack. *****************************************************************************/ int CVICALLBACK TCPServerCallback (unsigned handle, int event, int error, void *callbackData) { char inbuf[512], outbuf[300], command[80], path[256]; int file_size, update_rate, device, dataSize = 512, i, intvalue; float floatvalue; list * curr; struct msg_type bufdata; switch (event) { case TCP_CONNECT: TCPHandle = handle; SetCtrlVal (panelHandle, PANEL_HISTORY, "New connection established\n"); TCPConnect = 1; break; case TCP_DATAREADY: if ((dataSize = ServerTCPRead(TCPHandle, &bufdata, dataSize, 1000)) == -kTCP_ConnectionClosed) { SetCtrlVal (panelHandle, PANEL_HISTORY, "TCP Read Error - connection closed\n"); TCPConnect = 0; } /* extract the message from the buffer */ memcpy (inbuf, &bufdata.msg, bufdata.msglen-2); /* append a NULL so it looks like a string */ inbuf[bufdata.msglen-2]=0; sscanf (inbuf,"%s ", command); if (!strcmp (command,"INTERVAL")) { sscanf (inbuf,"%s %f", command, &floatvalue); SetCtrlVal (panelHandle, PANEL_INTERVAL, floatvalue); sprintf (bufdata.msg, "%s \n",inbuf); } else if (!strcmp (command, "FILE_SIZE")) { sscanf (inbuf,"%s %d", command, &intvalue);


136

APPENDIX G: Labwindows/CVI Source Code
SetCtrlVal (panelHandle, PANEL_FILE_SIZE, intvalue); sprintf (bufdata.msg, "%s \n",inbuf); } else if (!strcmp (command, "DEVICE")) { sscanf (inbuf,"%s %d", command, &intvalue); SetCtrlVal (panelHandle, PANEL_DEVICE, intvalue); sprintf (bufdata.msg, "%s \n",inbuf); DEVICE (panelHandle, PANEL_DEVICE, EVENT_COMMIT, NULL, NULL, NULL); } else if (!strcmp (command, "TIMESOURCE")) { sscanf (inbuf,"%s %d", command, &intvalue); SetCtrlVal (panelHandle, PANEL_TIMESOURCE, intvalue); sprintf (bufdata.msg, "%s \n",inbuf); } else if (!strcmp (command, "GO")) { sscanf (inbuf,"%s %d", command, &intvalue); SetCtrlVal (panelHandle, PANEL_GO, intvalue); sprintf (bufdata.msg, "%s \n",inbuf); START (panelHandle, PANEL_GO, EVENT_COMMIT, NULL, NULL, NULL); } else if (!strcmp (command, "AVERAGE")) { sscanf (inbuf,"%s %d", command, &intvalue); SetCtrlVal (panelHandle, PANEL_AVERAGE, intvalue); sprintf (bufdata.msg, "%s \n",inbuf); } else if (!strcmp (command, "LOGBASE")) { sscanf (inbuf,"%s %s", command, logbase); sprintf (bufdata.msg, "%s \n",inbuf); } else { sprintf (bufdata.msg, " invalid message\n"); } SetCtrlVal (panelHandle, PANEL_HISTORY, bufdata.msg); bufdata.msglen = strlen (bufdata.msg) + 2; bufdata.msgHD = MSGHD; if (ServerTCPWrite (TCPHandle, &bufdata, bufdata.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } break; case TCP_DISCONNECT: SetCtrlVal (panelHandle, PANEL_HISTORY, "Connection closed by client\n"); TCPConnect = 0; break;

} return (0); }


APPENDIX G: Labwindows/CVI Source Code

137

/***************************************************************************** Main Routine *****************************************************************************/ int main (int argc, char *argv[]) { list *curr; if (InitCVIRTE (0, argv, 0) == 0) return -1; /* load all panels into memory */ if ((panelHandle = LoadPanel (0, "panel.uir", PANEL)) < 0) return -1; if ((aboutHandle = LoadPanel (0, "panel.uir", ABOUT)) < 0) return -1; if ((menuHandle = LoadMenuBar (panelHandle, "panel.uir", MENU)) < 0) return -1; /* Set the compile date */ #ifdef __STDC__ SetCtrlVal (aboutHandle, ABOUT_DATE, __DATE__); #endif /* start the data acquisition thread */ CmtScheduleThreadPoolFunction (DEFAULT_THREAD_POOL_HANDLE, GetDataThread, NULL, NULL); /* bring up the main panel */ DisplayPanel (panelHandle); SetCtrlVal (panelHandle, PANEL_HISTORY, "Registering TCP Server on port 4321: "); if (RegisterTCPServer(4321, TCPServerCallback, NULL)<0) SetCtrlVal (panelHandle, PANEL_HISTORY, "Failed\n"); else SetCtrlVal (panelHandle, PANEL_HISTORY, "Successful\n"); /* run the GUI, so people can control things. */ RunUserInterface (); /* we're leaving, so close up behind us, and free any memory we've malloc'd */ while (head) { curr = head->next; free (head); head = curr; } return 0; }

/***************************************************************************** Shutdown Called when the user hits the quit button. *****************************************************************************/ int CVICALLBACK Shutdown (int panel, int control, int event, void *callbackData, int eventData1, int eventData2)


138
{ switch (event) { case EVENT_COMMIT: QuitUserInterface (0); break; } return 0; }

APPENDIX G: Labwindows/CVI Source Code

/***************************************************************************** Menu Code to make sense of the pulldown menus. *****************************************************************************/ void CVICALLBACK Menu(int menubar, int menuItem, void *callbackData, int panel) { switch (menuItem) { case MENU_FILE_LOGFILE: FileSelectPopup ("","*.csv","*.csv","Log File",VAL_OK_BUTTON, 0,0,1,1,logbase); /* we need to remove the .csv, as this is added later, along with the current date and time, when the file is first created. */ if (strchr(logbase,'.')) *strchr(logbase,'.')=NULL; break; case MENU_FILE_QUIT: QuitUserInterface (0); break; case MENU_HELP_ABOUT: DisplayPanel (aboutHandle); break; } }

/***************************************************************************** Dateset_In Provides input from a dataset without address translation. *****************************************************************************/ int Dataset_In(int ds_address, int monitor_point, int *data_in) { /* Error codes: 0 -1 -2 -3 success comms error dataset error invalid control point

*/ int message, err, response;


APPENDIX G: Labwindows/CVI Source Code
if (monitor_point < 0 || monitor_point > 511) return(-3); message = MONITOR + (ds_address << 25) + (monitor_point << 16); if (err = SendMessage(message)) return(err); if (err = ReadResponse(&response)) return(err); *data_in = (response & 0xffff); return(0); }

139

/***************************************************************************** Add_To_List Adds the current data to a linked list, checks whether we have enough data to archive, and if we do writes the list out to a file before trashing it. *****************************************************************************/ list* Add_To_List (list *head, char *time, double sec, double *data) { list *new, *curr; static list *last; int i, hours, minutes, seconds, file_size, dump, n; char *date, linebuf [256]; struct msg_type bufdata; GetCtrlVal (panelHandle, PANEL_FILE_SIZE, &file_size); /* create new list item */ new = malloc(sizeof(list)); /* copy values into item */ strcpy (new->time, time); for (i=0;i<16;i++) new->data[i]=data[i]; new->sec=sec; /* give item a null pointer */ new->next = NULL; /* is this the first time? yes - point head to item */ if (!head) { head = new; list_len = 0; } /* no - point last item to item */ else last->next = new; last = new; list_len ++; /* do we have enough items to offload to a file? */ if (list_len%10 == 0) { /* first check if it's time for a new file */ if (file_len>=file_size) { /* Generate the new filename, and write the header */ date = DateStr (); sscanf (head->time,"%d:%d:%d",&hours,&minutes,&seconds); sprintf (logpath, "%s-%s-%02d-%02d-%02d.csv", logbase, date, hours, minutes, seconds); if (!(logfile = fopen (logpath, "w"))) {


140

APPENDIX G: Labwindows/CVI Source Code
sprintf (bufdata.msg,"ERROR - Unable to open %s\n",logpath); SetCtrlVal (panelHandle, PANEL_HISTORY, bufdata.msg); bufdata.msglen = strlen (bufdata.msg) + 2; bufdata.msgHD = MSGHD; if (TCPConnect) { if (ServerTCPWrite (TCPHandle, &bufdata, bufdata.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } } else MessagePopup ("ERROR", "Cannot open file"); } else { file_len = 0; fprintf (logfile,"Water Vapour Radiometer Logfile\n"); fclose (logfile); sprintf (bufdata.msg,"Opened %s\n",logpath); SetCtrlVal (panelHandle, PANEL_HISTORY, bufdata.msg); bufdata.msglen = strlen (bufdata.msg) + 2; bufdata.msgHD = MSGHD; if (TCPConnect) { if (ServerTCPWrite (TCPHandle, &bufdata, bufdata.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } } ClearStripChart (panelHandle, PANEL_INPUTS); } } if (logfile = fopen (logpath, "a")) { /* Now offload the buffer to the file. Note that if we're unable to open the file, we don't worry about it, but just try again next time. This way, we're able to cope with ppl accessing the file we're writing to with no loss of data. */ for (dump=20;dump&&head;dump--) { /* we offload up to 20 elements at a time, or the whole list, whichever is less. This way, we don't risk missing the next read because we're busy dumping a large number of records, but are still able to "catch up" reasonably quickly, if we haven't been able to access the file for a while. */ fprintf (logfile, "%s, %f, ",head->time, head->sec); for (i=0;i<16;i++) fprintf (logfile, "%f, ",head->data[i]); fprintf (logfile, "\n"); curr = head->next; free (head); head = curr; list_len --; file_len ++; } /* close up behind us, so that others can access the file */ fclose (logfile);


APPENDIX G: Labwindows/CVI Source Code
sprintf (bufdata.msg,"Logged %d samples\n",file_len); GetNumTextBoxLines(panelHandle, PANEL_HISTORY, &n); if (n>1) { GetTextBoxLine(panelHandle, PANEL_HISTORY, n-2, linebuf); if (!strncmp(bufdata.msg,"Logged",6) && !strncmp(linebuf,"Logged",6)) DeleteTextBoxLine(panelHandle,PANEL_HISTORY,n-2); SetCtrlVal (panelHandle, PANEL_HISTORY, bufdata.msg); } bufdata.msglen = strlen (bufdata.msg) + 2; bufdata.msgHD = MSGHD; if (TCPConnect) { if (ServerTCPWrite (TCPHandle, &bufdata, bufdata.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } } } } return head; }

141

/***************************************************************************** TIMER Called when it's time to log a sample. *****************************************************************************/ int CVICALLBACK TIMER (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { getdataflag = 1; return (0); }

/***************************************************************************** GetDataThread Runs continuously as a separate thread. When getdataflag is set by main thread, it clears the flag, then gets a sample, and adds it to the list, as well as displaying it on the chart. Is able to deal with National Instruments DAQ cards (8 channel, 16 bit) as well as the AT WVR interface (16 channel, 24 bit). *****************************************************************************/ int CVICALLBACK GetDataThread (void *functionData) { struct msg_type bufdata; char *curr_time; char errstring[40]; int i, j, intdata, loworder, device, average, timesource, noise_interval,


142

APPENDIX G: Labwindows/CVI Source Code

//

// // // // // // // // // // // //

noise_en, err; short temp[8196], status = 0; short chanvector[8] = {0,1,2,3,4,5,6,7}; short gainvector[8] = {1,1,1,1,1,1,1,1}; double data[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; double curr_sec; for (;;) { if (getdataflag) { getdataflag = 0; GetCtrlVal (panelHandle, PANEL_DEVICE, &device); GetCtrlVal (panelHandle, PANEL_AVERAGE, &average); GetCtrlVal (panelHandle, PANEL_NOISE, &noise_interval); GetCtrlVal (panelHandle, PANEL_NOISE_EN, &noise_en); curr_time = TimeStr(); curr_sec = Timer(); if (device) { /* set the DAQ card process up */ SCAN_Setup (DAQ_Device, 8, chanvector,gainvector); /* SCAN_Start hangs if we give it 1 scan. For both cases, we take samples at 20 us intervals (50KHz), and scan each set at 200 us intervals, but for the single scan case, we actually take 2 scans and ignore the second. */ if (average==1) SCAN_Start (DAQ_Device, &temp[0], 16, 1, 20, 1, 200); else SCAN_Start (DAQ_Device, &temp[0], average*8, 1, 20, 1, 200); /* wait for the process to finish */ while (!status) DAQ_Check (DAQ_Device, &status, &i); /* average the result */ for (j=0;j

APPENDIX G: Labwindows/CVI Source Code
MessagePopup ("ERROR", "TCP write error."); } } } else { if (err = Dataset_In (DSA, 16, &loworder)) { data[i]=-11; sprintf (bufdata.msg, "Dataset_In returned %d\n", err); SetCtrlVal (panelHandle, PANEL_HISTORY, bufdata.msg); if (TCPConnect) { bufdata.msglen = strlen (bufdata.msg) + 2; bufdata.msgHD = MSGHD; if (ServerTCPWrite (TCPHandle, &bufdata, bufdata.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } } } else { intdata = (intdata * 256) + (loworder & 0x00ff)+1; if (intdata > 8388352) intdata -= 16777216; /* scale to volts */ data[i]=(double)intdata/(838860.8); } } } } PlotStripChart (panelHandle, PANEL_INPUTS, &data[0], 16, 0, 0, VAL_DOUBLE); head = Add_To_List (head, curr_time, curr_sec, &data[0]); } } return 0; }

143

/***************************************************************************** CLOSE_ABOUT Shuts down the about window. *****************************************************************************/ int CVICALLBACK CLOSE_ABOUT (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: HidePanel (aboutHandle); break; }


144
return 0; }

APPENDIX G: Labwindows/CVI Source Code

/***************************************************************************** CHART_SCALE Changes the scaling for the stripchart. *****************************************************************************/ int CVICALLBACK CHART_SCALE (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { double min, max, temp; switch (event) { case EVENT_COMMIT: GetCtrlVal (panel, PANEL_CHART_MIN, &min); GetCtrlVal (panel, PANEL_CHART_MAX, &max); if (min > max) { SetCtrlVal (panel, PANEL_CHART_MIN, max); SetCtrlVal (panel, PANEL_CHART_MAX, min); temp = min; min = max; max = temp; } SetAxisScalingMode (panel, PANEL_INPUTS, VAL_LEFT_YAXIS, VAL_MANUAL, min, max); break; } return 0; }

/***************************************************************************** DEVICE Input device change. *****************************************************************************/ int CVICALLBACK DEVICE (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { int device; switch (event) { case EVENT_COMMIT: GetCtrlVal (panel, PANEL_DEVICE, &device); if (device == 0) { SetCtrlVal (panel, PANEL_AVERAGE, 1); SetCtrlAttribute (panel, PANEL_AVERAGE, ATTR_DIMMED, 1); SetCtrlAttribute (panel, PANEL_INTERVAL, ATTR_MIN_VALUE, 0.2); } else { SetCtrlAttribute (panel, PANEL_AVERAGE, ATTR_DIMMED, 0); SetCtrlAttribute (panel, PANEL_INTERVAL, ATTR_MIN_VALUE, 0.05);


APPENDIX G: Labwindows/CVI Source Code
} break; } return 0; }

145

/***************************************************************************** START Initialises inputs when we start recording. *****************************************************************************/ int CVICALLBACK START (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { int device, go, i; double interval; list *curr; struct msg_type bufdata; switch (event) { case EVENT_COMMIT: GetCtrlVal (panel, PANEL_DEVICE, &device); GetCtrlVal (panel, PANEL_GO, &go); GetCtrlVal (panelHandle, PANEL_INTERVAL, &interval); SetCtrlAttribute (panelHandle, PANEL_TIMER, ATTR_INTERVAL, interval); SetCtrlAttribute (panelHandle, PANEL_TIMER, ATTR_ENABLED, go); if (!device && go) { Initialise_Dataset(DSA, port, BAUD); SetComTime (port, 0.5); } if (!go) { if (logfile = fopen (logpath, "a")) { /* Offload the buffer to the file. */ while (head) { fprintf (logfile, "%s, %f, ",head->time, head->sec); for (i=0;i<8;i++) fprintf (logfile, "%f, ",head->data[i]); fprintf (logfile, "\n"); curr = head->next; free (head); head = curr; } /* close up behind us. */ fclose (logfile); /* re-initialise file and list lengths */ file_len = 99999999; list_len = 0; SetCtrlVal (panelHandle, PANEL_HISTORY, "Data Collection Stopped\n");


146

APPENDIX G: Labwindows/CVI Source Code
sprintf (bufdata.msg,"Data Collection Stopped\n"); } } else { SetCtrlVal (panelHandle, PANEL_HISTORY, "Data Collection Started\n"); sprintf (bufdata.msg,"Data Collection Started\n"); } if (TCPConnect) { bufdata.msglen = strlen (bufdata.msg) + 2; bufdata.msgHD = MSGHD; if (ServerTCPWrite (TCPHandle, &bufdata, bufdata.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } } break;

} return 0; }

G.4
G.4.1

Water Vapour Radiometer Client
wvr client.c

/***************************************************************************** Water Vapour Radiometer Client Allows us to remotely control the water vapour radiometer data collection process.. Version: Commenced: Last Revised: Author: 0.1 5 Sep 2000 5 Sep 2000 Suzy Jackson

*****************************************************************************/ #include #include #include #include #include "client.h"

#define MSGHD 71

/***************************************************************************** A data structure to hold request/control data. *****************************************************************************/


APPENDIX G: Labwindows/CVI Source Code

147

struct msg_type { char msgHD; unsigned char msglen; char msg[512]; };

/***************************************************************************** Prototypes. *****************************************************************************/ int CVICALLBACK Shutdown (int panel, int control, int event, void *callbackData, int eventData1, int eventData2); int CVICALLBACK SEND (int panel, int control, int event, void *callbackData, int eventData1, int eventData2); int CVICALLBACK TCPClientCallback (unsigned handle, int event, int error, void *callbackData); int CVICALLBACK CONNECT (int panel, int control, int event, void *callbackData, int eventData1, int eventData2); void CVICALLBACK Menu (int menuBar, int menuItem, void *callbackData, int panel); int CVICALLBACK CLOSE_ABOUT (int panel, int control, int event, void *callbackData, int eventData1, int eventData2);

/***************************************************************************** Global Variables. *****************************************************************************/ int panelHandle, aboutHandle, menuHandle, TCPHandle;

/***************************************************************************** Main program. *****************************************************************************/ int main (int argc, char *argv[]) { char miscstring [300]; if (InitCVIRTE (0, argv, 0) == 0) /* Needed if linking in external compiler */ return -1; /* out of memory */ if ((panelHandle = LoadPanel (0, "client.uir", PANEL)) < 0) return -1; if ((aboutHandle = LoadPanel (0, "client.uir", ABOUT)) < 0) return -1; if ((menuHandle = LoadMenuBar (panelHandle, "client.uir", MENU)) < 0) return -1; if (argc == 2) {


148

APPENDIX G: Labwindows/CVI Source Code
SetWaitCursor (1); if (ConnectToTCPServer (&TCPHandle, 4321, argv[1], TCPClientCallback, NULL, 5000) <0) { MessagePopup ("ERROR", "Unable to connect to server."); SetCtrlVal (panelHandle, PANEL_CONNECT, 0); } else { SetCtrlVal (panelHandle, PANEL_HISTORY, "Connected to "); SetCtrlVal (panelHandle, PANEL_HISTORY, argv[1]); SetCtrlVal (panelHandle, PANEL_HISTORY, "\n"); sprintf (miscstring,"WVR Client - %s",argv[1]); SetPanelAttribute (panelHandle, ATTR_TITLE, miscstring); SetCtrlVal (panelHandle, PANEL_CONNECT, 1); } SetWaitCursor (0);

} DisplayPanel (panelHandle); RunUserInterface (); return 0; }

/***************************************************************************** Shutdown - called when user hits the quit button. *****************************************************************************/ int CVICALLBACK Shutdown (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: QuitUserInterface (0); break; } return 0; }

/***************************************************************************** Send - sends data to the server. *****************************************************************************/ int CVICALLBACK SEND (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { int intdata; double doubledata; struct msg_type message; switch (event) {


APPENDIX G: Labwindows/CVI Source Code
case EVENT_COMMIT: switch (control) { case PANEL_INTERVAL: GetCtrlVal (panelHandle, PANEL_INTERVAL, &doubledata); sprintf (message.msg,"INTERVAL %f",doubledata); break; case PANEL_FILE_SIZE: GetCtrlVal (panelHandle, PANEL_FILE_SIZE, &intdata); sprintf (message.msg,"FILE_SIZE %d",intdata); break; case PANEL_DEVICE: GetCtrlVal (panelHandle, PANEL_DEVICE, &intdata); if (intdata == 0) { SetCtrlVal (panel, PANEL_AVERAGE, 1); SetCtrlAttribute (panel, PANEL_AVERAGE, ATTR_DIMMED, 1); SetCtrlAttribute (panel, PANEL_INTERVAL, ATTR_MIN_VALUE, 0.2); } else { SetCtrlAttribute (panel, PANEL_AVERAGE, ATTR_DIMMED, 0); SetCtrlAttribute (panel, PANEL_INTERVAL, ATTR_MIN_VALUE, 0.05); } sprintf (message.msg,"DEVICE %d",intdata); break; case PANEL_TIMESOURCE: GetCtrlVal (panelHandle, PANEL_TIMESOURCE, &intdata); sprintf (message.msg,"TIMESOURCE %d",intdata); break; case PANEL_GO: GetCtrlVal (panelHandle, PANEL_GO, &intdata); sprintf (message.msg,"GO %d",intdata); break; case PANEL_AVERAGE: GetCtrlVal (panelHandle, PANEL_AVERAGE, &intdata); sprintf (message.msg,"AVERAGE %d",intdata); break; } /* create the message */ message.msglen = strlen (message.msg) + 2; message.msgHD = MSGHD; /* send it */ if (ClientTCPWrite (TCPHandle, &message, message.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } break; } return 0;

149


150
}

APPENDIX G: Labwindows/CVI Source Code

/***************************************************************************** TCPClientCallback - deciphers server responses. *****************************************************************************/ int CVICALLBACK TCPClientCallback (unsigned handle, int event, int error, void *callbackData) { struct msg_type bufdata; int dataSize = 512, n; char *temp, inbuf[256], linebuf[256]; TCPHandle = handle; switch (event) { case TCP_DATAREADY: if ((dataSize = ClientTCPRead(TCPHandle, &bufdata, dataSize, 1000)) == -kTCP_ConnectionClosed) { SetCtrlVal (panelHandle, PANEL_HISTORY, "TCP Read Error - connection closed\n"); } /* extract the message from the buffer */ memcpy (inbuf, &bufdata.msg, bufdata.msglen-2); /* append a NULL so it looks like a string */ inbuf[bufdata.msglen-2]=0; GetNumTextBoxLines(panelHandle, PANEL_HISTORY, &n); if (n>1) { GetTextBoxLine(panelHandle, PANEL_HISTORY, n-2, linebuf); if (!strncmp(inbuf,"Logged",6) && !strncmp(linebuf,"Logged",6)) DeleteTextBoxLine(panelHandle,PANEL_HISTORY,n-2); SetCtrlVal (panelHandle, PANEL_HISTORY, inbuf); } if (n>100) DeleteTextBoxLine(panelHandle, PANEL_HISTORY, 0); break; case TCP_DISCONNECT: MessagePopup ("NOTE", "Server has closed connection."); SetCtrlVal (panelHandle, PANEL_CONNECT, 0); break; } return (0); }

/***************************************************************************** Connect - manages connections to the server. *****************************************************************************/ int CVICALLBACK CONNECT (int panel, int control, int event, void *callbackData, int eventData1, int eventData2)


APPENDIX G: Labwindows/CVI Source Code
{ int connect; char hoststring [256], miscstring [300]; switch (event) { case EVENT_COMMIT: GetCtrlVal (panelHandle, PANEL_CONNECT, &connect); if (connect == 1) { PromptPopup("Enter Host Name", "Please type the name of the host machine.\n(eg wvrca03-cj)", hoststring, 255); SetWaitCursor (1); if (ConnectToTCPServer (&TCPHandle, 4321, hoststring, TCPClientCallback, NULL, 5000) <0) { MessagePopup ("ERROR", "Unable to connect to server."); SetCtrlVal (panelHandle, PANEL_CONNECT, 0); } else { SetCtrlVal (panelHandle, PANEL_HISTORY, "Connected to "); SetCtrlVal (panelHandle, PANEL_HISTORY, hoststring); SetCtrlVal (panelHandle, PANEL_HISTORY, "\n"); sprintf (miscstring,"WVR Client - %s",hoststring); SetPanelAttribute (panelHandle, ATTR_TITLE, miscstring); } SetWaitCursor (0); } else { DisconnectFromTCPServer (TCPHandle); SetPanelAttribute (panelHandle, ATTR_TITLE, "WVR Client"); SetCtrlVal (panelHandle, PANEL_HISTORY, "Disconnected from server\n"); } } return 0; }

151

/***************************************************************************** Menu - deals with the pulldown menus. *****************************************************************************/ void CVICALLBACK Menu (int menuBar, int menuItem, void *callbackData, int panel) { int err; char logbase [512]; struct msg_type message; switch (menuItem) { case MENU_FILE_QUIT: QuitUserInterface (0); break; case MENU_FILE_LOGFILE:


152

APPENDIX G: Labwindows/CVI Source Code
PromptPopup("Enter Filename", "Please enter the filename prefix.\nThe system will append a date and time field to this for each file.\n eg: wvrdata-ca03", logbase, 256); sprintf (message.msg,"LOGBASE %s",logbase); message.msglen = strlen (message.msg) + 2; message.msgHD = MSGHD; if (ClientTCPWrite (TCPHandle, &message, message.msglen, 1000)<0) { MessagePopup ("ERROR", "TCP write error."); } break; case MENU_HELP_ABOUT: DisplayPanel (aboutHandle); default: break;

} }

/***************************************************************************** CLOSE_ABOUT Shuts down the about window. *****************************************************************************/ int CVICALLBACK CLOSE_ABOUT (int panel, int control, int event, void *callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: HidePanel (aboutHandle); break; } return 0; }