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Correlator Update
17/09/02
The "Correlator Team" (Tim Adams, Nyima Warr & Dimiter Nedialkov) was formed
on the 13/8/02, with different members of the group having varying levels of
knowledge about the project to date. Thus a lot of time so far has been
spent in understanding the design and its implications to a real world
application. Having this understanding under our belt, the correlator team
has been able to make progress in software usage, hardware design and
project specifications.
The Way Forward
The roles of the different members in the group could be described as
follows:
Nyima: Advisory/Xilinx Design
Tim: Xilinx Design/PCB Design
Dimiter: Xilinx Optimisation of XMAC units.
Due to the necessity to demonstrate a working Correlator unit by mid 2003,
the following approach has been decided for the project:
1) Dimiter will work on a highly optimized version of the XMAC unit,
using custom build lookup table logic. This is his thesis topic and thus is
highly specialized. Dimiter is aiming to fit a large number of XMAC's into
an FPGA (.approx 64), however will not know if this is possible until
completion of his design. The benefits of this would be that the chip could
possibly be run a little slower, or an FPGA could process more data, thus
less FPGA's required per board. Due to the fact that Dimiter's design will
not be finished in the near future, a backup plan has been implemented.
2) Tim has design an XMAC unit using Xilinx Coregen components. The
size of the XMAC matches predictions by Lynn Urry and Dan Werthimer thus in
total 16 XMAC units could fit into an FPGA comfortably. This design is
currently being developed as a testing/backup design and if necessary could
be used in the demonstrator. It will be designed in a black box fashion, ie.
The inputs and outputs will be standard thus if Dimiter's design is proven
to work better, it could be substituted simply and quickly.
Software
The group has obtained Xilinx Foundation software (4 Licenses) for the FPGA
design. Quite some time has been spent getting used to the new design
methodology implemented in this software, as well as the inherent bugs it
contains. Tim has been designing using Schematic Capture, whereas Dimiter
has been using VHDL.
Nyima has organised to order some copies of Protel DXP to perform the PCB
design.
Hardware
We have acquired (via Xilinx), four Digilent Experimenter's boards. The
boards offer the facilities of easy programmability and multiple IO options.
The boards use Spartan 2S200 FPGA's, however, the specifications of a
Spartan 2 and SE and are quite similar, thus the boards will be useful in
simple proof of design and concepts.
XMACS
As mentioned above, the XMAC units are being approached on two fronts.
Dimiter is hoping to outdo the optimization capabilities of LogiCore, and
design an XMAC array that is based around Lookup table multiplier logic.
Essentially, Dimiter's design uses four multiplier interfaces (ie. 1 complex
multiply) that reference the one lookup table (implemented in Block Select
SDRAM - thus less CLB's required per XMAC unit). Results from the
calculation will be accumulated for 1s using Ram implemented in CLB's.
Tim has designed a simpler implementation using customised LogiCore
components. Four multipliers accept the four components of the two complex
numbers to be multiplied. Following multiplication, the respective numbers
are added or subtracted and summed over a period of 64 samples. Following
this the results are pipeline multiplexed onto 1 SDRAM Block, where they are
accumulated for 1s. The current implementation statistics are as follows
(per XMAC):
Number of Slices: 146 out of 3,072 4%
Number of Slice Flip Flops: 247 out of 6,144 4%
Number of 4 input LUTs: 221 out of 6,144 3%
Number of Block RAMs: 1 out of 16 6%
Total equivalent gate count for design: 21,004
Therefore 16 XMACS would occupy 146x16 slices = 2336 slices. This is only
76% of the total space available, thus room would remain for any control
logic required.
PCB
The current thinking is that a board with 16 FPGA's will be designed. This
is catering for the base design of 4X4 XMAC FPGA's. However, all available
IO lines will be routed to tracks, thus if a more optimised design is proven
to work, then it would be a simple case of addressing the un-used PCB
traces.
Interfaces
The two interfaces that the correlator needs to deal with are the input and
the output. It has been decided that the input will be implemented using
LVDS signals on 100ohm twisted pair lines. Thus, the Delay units will have a
20 Way Twisted pair LVDS output that will contain an 8 bit parallel bus, 1
clock and 1 Index Signal. The correlator will have facilities to receive 12
such cables thus 96IF's. The physical issues involved in putting 12 x 20 Way
connectors on the edge of a PCB are yet to be tackled, however one thought
has been to include a Correlator daughter board, to cope with the extensive
IO.
An output standard is yet to be thoroughly looked at or discussed. Some
suggestions have been:
· USB
· Ethernet
· Parallel
· Serial
· PCI Bus
· Firewire (IEEE 1394)
· ATNF PCI Bus Interface
Discussions are to be held soon to discuss this issue, after which the above
list should be narrowed to a number of options to be explored.
Tim Adams
17 September 2002
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