Äîêóìåíò âçÿò èç êýøà ïîèñêîâîé ìàøèíû. Àäðåñ îðèãèíàëüíîãî äîêóìåíòà : http://www.apo.nmsu.edu/arc35m/Instruments/ARCTIC/Development/ImagerPDR/DS18B20.pdf Äàòà èçìåíåíèÿ: Thu Dec 5 20:44:29 2013 Äàòà èíäåêñèðîâàíèÿ: Thu Feb 27 21:04:24 2014 Êîäèðîâêà: Ïîèñêîâûå ñëîâà: helix nebula

AVAILABLE

DS18B20 Programmable Resolution 1-Wire Digital Thermometer
DESCRIPTION
The DS18B20 digital thermo meter provides 9-bit to 12-bit Celsius temperature measurements and has an alarm funct ion wit h nonvo lat ile userprogrammable upper and lower trigger points. The DS18B20 communicates over a 1-Wire bus that by definit io n requires only one data line (and ground) for communicat ion wit h a central microprocessor. It has an operating temperature range o f -55°C to +125°C and is accurate to 0.5 C over the range o f -10°C to +85°C. In addit ion, the DS18B20 can derive power direct ly fro m the data line ("parasite power"), eliminat ing the need for an external power supply. Each DS18B20 has a unique 64-bit serial code, which allows mult iple DS18B20s to funct ion on the same 1-Wire bus. Thus, it is simple to use one microprocessor to control many DS18B20s distributed over a large area. Applicat ions that can benefit fro m this feature include HVAC environmental controls, temperature monitoring systems inside buildings, equipment, or machinery, and process mo nitoring and control systems.
User-Definable Nonvolatile (NV) Alarm Settings Alarm Search Command Identifies and Addresses Devices Whose Temperature is Outside Programmed Limits (Temperature Alarm Condition) Available in 8-Pin SO (150 mils), 8-Pin SOP, and 3-Pin TO-92 Packages Software Compatible with the DS1822 Applications Include Thermostatic Controls, Industrial Systems, Consumer Products, Thermometers, or Any Thermally Sensitive System

PIN CONFIGURATIONS
MAXIM 18B20 123 N.C. N.C. VDD DQ
1 8

N.C. N.C. N.C. GND

MAXIM 18B20

2 3 4

7 6 5

SO (150 mils) (DS18B20Z)

FEATURES
Unique 1-Wire® Interface Requires Only One Port Pin for Communication Each Device has a Unique 64-Bit Serial Code Stored in an On-Board ROM Multidrop Capability Simplifies Distributed Temperature-Sensing Applications Requires No External Components Can Be Powered from Data Line; Power Supply Range is 3.0V to 5.5V Measures Temperatures from -55°C to +125°C (-67°F to +257°F) 0.5 C Accuracy from -10°C to +85°C Thermometer Resolution is User Selectable from 9 to 12 Bits Converts Temperature to 12-Bit Digital Word in 750ms (Max)
GND DQ VDD DQ N.C. N.C. GND
1 2 3 4 8 7 6 5

VDD N.C. N.C. N.C.

123
(BOTTOM VIEW )

SOP (DS18B20U)

18B20

TO-92 (DS18B20)

1-Wire is a registered tr ademark of Max im Integr ated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct .com. at 1-888-629-4642, or visit Maxim's website at www.maxim

REV: 042208


DS18B20

ORDERING INFORMATION
DS DS DS DS DS DS DS DS DS DS DS DS DS DS PART 18B20 18B20+ 18B20/T&R 18B20+T&R 18B20-SL/T&R 18B20-SL+T&R 18B20U 18B20U+ 18B20U/T&R 18B20U+T&R 18B20Z 18B20Z+ 18B20Z/T&R 18B20Z+T&R TEMP -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t -55 C t RANG o +125 o +125 o +125 o +125 o +125 o +125 o +125 o +125 o +125 o +125 o +125 o +125 o +125 o +125 E C C C C C C C C C C C C C C PIN-PACKAGE 3 TO-92 3 TO-92 3 TO-92 (2000 Piece) 3 TO-92 (2000 Piece) 3 TO-92 (2000 Piece)* 3 TO-92 (2000 Piece)* 8 SOP 8 SOP 8 SOP (3000 Piece) 8 SOP (3000 Piece) 8 SO 8 SO 8 SO (2500 Piece) 8 SO (2500 Piece) TOP MARK 18B20 18B20 18B20 18B20 18B20 18B20 18B20 18B20 18B20 18B20 DS18B20 DS18B20 DS18B20 DS18B20

+Denotes a lead-fr ee package. A "+" w ill appear on the top mark of lead-free packages. T&R = Tape and reel. *TO-92 packages in tape and reel can be or der ed w ith straight or formed leads. Choose " SL" for straight leads. Bulk TO-92 or ders are s traight leads only.

PIN DESCRIPTION
PIN SO 1, 2, 6, 7, 8 3 4 5 SOP 2, 3, 5, 6, 7 8 1 4 TO-92 -- 3 2 1 NAME N.C. VDD DQ GND No Connect ion Optional VDD. VDD must be grounded for operation in parasite power mode. Data Input/Output. Open-drain 1-Wire interface pin. Also provides power to the device when used in parasite power mode (see the Powering the DS18B20 section.) Ground FUNCTION

OVERVIEW
Figure 1 shows a block diagram o f the DS18B20, and pin descriptions are given in the Pin Description table. The 64-bit ROM stores the device's unique serial code. The scratchpad memory contains the 2-byte temperature register that stores the digital output from the temperature sensor. In addit ion, the scratchpad provides access to the 1-byte upper and lower alarm trigger registers (TH and TL) and the 1-byt e configuration register. The configuration register allows the user to set the resolut ion o f the temperatureto-digital conversio n to 9, 10, 11, or 12 bits. The TH, TL, and configurat ion registers are nonvolat ile (EEPROM), so they will retain data when the device is powered down. The DS18B20 uses Maxim's exclusive 1-Wire bus protocol that implements bus co mmunicat ion using one control signal. The control line requires a weak pullup resistor since all devices are linked to the bus via a 3-state or open-drain port (the DQ pin in the case o f the DS18B20). In this bus system, the microprocessor (the master device) ident ifies and addresses devices on the bus using each device's unique 64-bit code. Because each device has a unique code, the number of devices that can be addressed on one
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DS18B20

bus is virtually unlimited. The 1-Wire bus protocol, including detailed explanat ions o f the co mmands and "t ime slots," is covered in the 1-Wire Bus System section. Another feature of the DS18B20 is the abilit y to operate without an external power supply. instead supplied through the 1-Wire pullup resist or via the DQ pin when the bus is high. The signal also charges an internal capacitor (CPP), which then supplies power to the device when t low. This method of deriving power from the 1-Wire bus is referred to as "parasite power alternat ive, the DS18B20 may also be powered by an external supply on VDD. Figure 1. DS18B20 Block Diagram
VPU
4.7k
PAR ASITE POWER CIRCUIT

Power is high bus he bus is ." As an

MEMORY CONTROL LOGIC

DS18B20
TEMPER ATU RE SENSOR

DQ
INTERN AL VDD 64-BIT R OM AND 1-Wire PORT

GND

C

PP

SCR AT CHPAD

AL ARM HIGH TRIGGER (TH) REGISTER (EEPR OM) AL ARM LOW TRIGGER (TL) REGISTER (EEPR OM)

VDD

POWERSUPPLY SENSE

CONFIGUR ATI ON R EGISTER (EEPR OM) 8-BIT CRC GEN ER AT OR

OPERATION--MEASURING TEMPERATURE
The core funct ionalit y o f the DS18B20 is its direct-to-digital temperature sensor. The reso lution of the temperature sensor is user-configurable to 9, 10, 11, or 12 bits, corresponding to increments of 0.5 C, 0.25 C, 0.125 C, and 0.0625 C, respectively. The default reso lution at power-up is 12-bit. The DS18B20 powers up in a low-power idle state. To init iate a temperature measurement and A-to-D conversio n, the master must issue a Convert T [44h] command. Fo llowing the conversion, the result ing thermal data is stored in the 2-byte temperature register in the scratchpad memory and the DS18B20 returns to its idle state. If the DS18B20 is powered by an external supply, the master can issue "read time slots" (see the 1-Wire Bus System sect ion) after the Convert T command and the DS18B20 will respond by transmitting 0 while the temperature conversio n is in progress and 1 when the conversio n is done. If the DS18B20 is powered with parasite power, this notificat ion technique cannot be used since the bus must be pulled hig h by a strong pullup during the ent ire temperature conversio n. The bus requirements for parasite power are explained in detail in the Po wering the DS18B20 section. The DS18B20 output temperature data is calibrated in degrees Celsius; for Fahrenheit applicat ions, a lookup table or conversio n routine must be used. The temperature data is stored as a 16-bit sign-extended two's complement number in the temperature register (see Figure 2). The sign bits (S) indicate if the temperature is posit ive or negat ive: for posit ive numbers S = 0 and for negat ive numbers S = 1. If the DS18B20 is configured for 12-bit reso lut ion, all bits in the temperature register will contain valid data. For 11-bit resolut ion, bit 0 is undefined. For 10-bit reso lut ion, bits 1 and 0 are undefined, and for 9-bit resolut ion bits 2, 1, and 0 are undefined. Table 1 gives examples of digital output data and the corresponding temperature reading for 12-bit resolution conversio ns.
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DS18B20

Figure 2. Temperature Register Format
BIT 7 3 2 BIT 15 MS BYTE
S = S IGN

LS BYTE

BIT 6 22 BIT 14 S

BIT 5 21 BIT 13 S

BIT 4 20 BIT 12 S

BIT 3 2-1 BIT 11 S

BIT 2 2-2 BIT 10 2
6

BIT 1 2-3 BIT 9 2
5

BIT 0 2-4 BIT 8 24

S

Table 1. Temperature/Data Relationship TEMPERATURE ( C) +125 +85* +25.0625 +10.125 +0.5 0 -0.5 -10.125 -25.0625 -55 DIGITAL OUTPUT (BINARY) 0000 0111 1101 0000 0000 0101 0101 0000 0000 0001 1001 0001 0000 0000 1010 0010 0000 0000 0000 1000 0000 0000 0000 0000 1111 1111 1111 1000 1111 1111 0101 1110 1111 1110 0110 1111 1111 1100 1001 0000 DIGITAL OUTPUT (HEX) 07D0h 0550h 0191h 00A2h 0008h 0000h FFF8h FF5Eh FE6Fh FC90h

*The power -on res et value of the temperature register is +85°C .

OPERATION--ALARM SIGNALING
After the DS18B20 performs a temperature conversion, the temperature value is co mpared to the userdefined two's co mplement alarm trigger values stored in the 1-byte TH and TL registers (see Figure 3). The sign bit (S) indicates if t he value is posit ive or negative: for posit ive numbers S = 0 and for negative numbers S = 1. The TH and TL registers are nonvo lat ile (EEPROM) so they will retain data when the device is powered down. TH and TL can be accessed through bytes 2 and 3 of the scratchpad as explained in the Memory sect ion. Figure 3. TH and TL Register Format
BIT 7 S BIT 6 6 2 BIT 5 5 2 BIT 4 4 2 BIT 3 3 2 BIT 2 2 2 BIT 1 1 2 BIT 0 0 2

Only bit s 11 through 4 o f the temperature register are used in the TH and TL co mparison since TH and TL are 8-bit registers. If the measured temperature is lower than or equal to TL or higher than or equal to TH, an alarm condit ion exists and an alarm flag is set inside the DS18B20. This flag is updated after ever y temperature measurement; therefore, if the alarm condit ion goes away, the flag will be turned off after the next temperature conversio n.
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DS18B20

The master device can check the alarm flag status of all DS18B20s on the bus by issuing an Alarm Search [ECh] co mmand. Any DS18B20s wit h a set alarm flag will respond to the co mmand, so the master ca n determine exact ly which DS18B20s have experienced an alarm condit io n. If an alarm condit ion exist s and the TH or TL settings have changed, another temperature conversio n should be done to validate the alarm condit io n.

POWERING THE DS18B20
The DS18B20 can be powered by an external supply on the VDD pin, or it can operate in "parasite power" mode, which allows the DS18B20 to funct ion wit hout a local external supply. Parasite power is ver y useful for applicat ions that require remote temperature sensing or that are very space constrained. Figure 1 shows the DS18B20's parasite-power control circuitry, which "steals" power from the 1-Wire bus via the DQ pin when the bus is high. The stolen charge powers the DS18B20 while the bus is high, and so me o f the charge is stored on the parasite power capacitor (CPP) to provide power when the bus is low. When the DS18B20 is used in parasite power mode, the VDD pin must be connected to ground. In parasite power mode, the 1-Wire bus and CPP can provide sufficient current to the DS18B20 for most operations as lo ng as the specified t iming and vo ltage requirements are met (see the DC Electrical Characteristics and AC Electrical Characteristics). However, when the DS18B20 is performing temperature conversio ns or copying data fro m the scratchpad memory to EEPROM, the operating current can be as high as 1.5mA. This current can cause an unacceptable vo ltage drop across the weak 1-Wire pullup resistor and is more current than can be supplied by CPP. To assure that the DS18B20 has sufficient supply current, it is necessary to provide a strong pullup on the 1-Wire bus whenever temperature conversio ns are taking place or data is being copied fro m the scratchpad to EEPROM. This can be accomplished by using a MOSFET to pull the bus directly to the rail as shown in Figure 4. The 1-Wire bus must be switched to the strong pullup wit hin 10 s (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus must be held high by the pullup for the duration of the conversion (tCONV) or data transfer (tWR = 10ms). No other activit y can take place on the 1-Wire bus while the pullup is enabled. The DS18B20 can also be powered by the convent ional method of connecting an external power supp ly to the VDD pin, as shown in Figure 5. The advantage of this method is that the MOSFET pullup is not required, and the 1-Wire bus is free to carry other traffic during the temperature conversio n time. The use o f parasite power is not recommended for temperatures above +100 C since the DS18B20 ma y not be able to sustain co mmunicat ions due to the higher leakage currents that can exist at these temperatures. For applicat ions in which such temperatures are likely, it is strongly reco mmended that the DS18B20 be powered by an external power supply. In so me situat ions the bus master may not know whether the DS18B20s on the bus are parasite powered or powered by external supplies. The master needs this information to determine if the strong bus pullup should be used during temperature conversio ns. To get this information, the master can issue a Skip ROM [CCh] co mmand fo llowed by a Read Power Supply [B4h] command fo llowed by a "read time slot". During the read t ime slot, parasite powered DS18B20s will pull the bus low, and externally powered DS18B20s will let the bus remain high. If the bus is pulled low, the master knows that it must supply the strong pullup on the 1-Wire bus during temperature conversio ns.

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DS18B20

Figure 4. Supplying the Parasite-Powered DS18B20 During Temperature Conversions
V
PU

DS18B20 P
V
PU

GND DQ V 4.7k 1-Wire BUS

DD

TO OTHER 1-WIRE DEVICES

Figure 5. Powering the DS18B20 with an External Supply

P

V

PU

DS18B20
GND DQ V 4.7k 1-Wire BUS
DD

V

DD

(EXTERNAL SUPPLY)

TO OTHER 1-WIRE DEVICES

64-BIT LASERED ROM CODE
Each DS18B20 contains a unique 64­bit code (see Figure 6) stored in ROM. The least significant 8 bit s of the ROM code contain the DS18B20's 1-Wire family code: 28h. The next 48 bits contain a unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated fro m the first 56 bit s of the ROM code. A detailed explanat ion of the CRC bits is provided in the CRC Generation sect ion. The 64-bit ROM code and associated ROM function control logic allo w the DS18B20 to operate as a 1-Wire device using the protocol detailed in the 1-Wire Bus System sect ion. Figure 6. 64-Bit Lasered ROM Code
8-BIT CRC MSB LSB 48-BIT SERIAL NUMBER MSB LSB 8-BIT FAMILY CODE (28h) MSB LSB

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DS18B20

MEMORY
The DS18B20's memory is organized as shown in Figure 7. The memory consists o f an SRAM scratchpad with nonvo lat ile EEPROM storage for the high and low alarm trigger registers (TH and TL) and configuration register. Note that if the DS18B20 alarm function is not used, the TH and TL registers can serve as general-purpose memory. All memo ry co mmands are described in detail in the DS18B20 Function Commands sect ion. Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register, respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Byte 4 contains the configuration register data, which is explained in detail in the Configuration Register section. Bytes 5, 6, and 7 are reserved for internal use by the device and cannot be overwritten. Byte 8 o f the scratchpad is read-only and contains the CRC code for bytes 0 through 7 o f the scratchpad. The DS18B20 generates this CRC using the method described in the CRC Generation sect ion. Data is written to bytes 2, 3, and 4 o f the scratchpad using the Write Scratchpad [4Eh] command; the data must be transmitted to the DS18B20 starting with the least significant bit o f byte 2. To verify data integrit y, the scratchpad can be read (using the Read Scratchpad [BEh] co mmand) after the data is written. When reading the scratchpad, data is transferred over the 1-Wire bus starting wit h the least significant bit o f byte 0. To transfer the TH, TL and configuration data from the scratchpad to EEPROM, the master must issue the Copy Scratchpad [48h] command. Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM data is reloaded into the corresponding scratchpad locat ions. Data can also be reloaded fro m EEPROM to 2 the scratchpad at any time using the Recall E [B8h] co mmand. The master can issue read time slots fo llo wing the Recall E2 command and the DS18B20 will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. Figure 7. DS18B20 Memory Map SCRATCHPAD (POWER-UP STATE) Byte 0 Temperature LSB (50h) (85°C) Byte 1 Temperature MSB (05h) Byte 2 TH Register or User Byte 1* Byte 3 TL Register or User Byte 2* Byte 4 Configuration Register* Byte 5 Reserved (FFh) Byte 6 Reserved Byte 7 Reserved (10h) Byte 8 CRC* *Powerup state depends on value(s) stored in EEPROM.

EEPROM TH Register or User Byte 1 TL Register or User Byte 2 Configuration Register

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DS18B20

CONFIGURATION REGISTER
Byte 4 o f the scratchpad memory contains the configuration register, which is organized as illustrated in Figure 8. The user can set the conversio n reso lutio n o f the DS18B20 using the R0 and R1 bits in this register as shown in Table 2. The power-up default of these bits is R0 = 1 and R1 = 1 (12-bit reso lutio n). Note that there is a direct tradeoff between reso lution and conversio n t ime. Bit 7 and bits 0 to 4 in the configuration register are reserved for internal use by the device and cannot be overwritten. Figure 8. Configuration Register

BIT 7 0

BIT 6 R1

BIT 5 R0

BIT 4 1

BIT 3 1

BIT 2 1

BIT 1 1

BIT 0 1

Table 2. Thermometer Resolution Configuration R1 0 0 1 1 R0 0 1 0 1 RESOLUTION (BITS) 9 10 11 12 MAX CONVERSION TIME 93.75ms (tCONV/8) 187.5ms (tCONV/4) 375ms (tCONV/2) 750ms (tCONV)

CRC GENERATION

CRC bytes are provided as part of the DS18B20's 64-bit ROM code and in the 9th byte o f the scratchpad memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in the most significant byte of the ROM. The scratchpad CRC is calculated fro m the data stored in the scratchpad, and therefore it changes when the data in the scratchpad changes. The CRCs provide the bus master with a method of data validat ion when data is read fro m the DS18B20. To verify that data has been read correctly, the bus master must re-calculate the CRC fro m the received data and then co mpare this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for scratchpad reads). If the calculated CRC matches the read CRC, the data has been received error free. The co mparison o f CRC values and the decis io n to continue wit h an operation are determined ent irely by the bus master. There is no circuitry ins ide the DS18B20 that prevents a co mmand sequence fro m proceeding if the DS18B20 CRC (ROM or scratchpad) does not match the value generated by the bus master. The equivalent polyno mial funct ion of the CRC (ROM or scratchpad) is: CRC = X8 + X5 + X4 + 1 The bus master can re-calculate the CRC and co mpare it to the CRC values fro m the DS18B20 using the polyno mial generator shown in Figure 9. This circuit consists of a shift register and XOR gates, and the shift register bits are init ialized to 0. Starting wit h the least significant bit o f the ROM code or the least significant bit o f byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After shift ing in the 56th bit fro m the ROM or the most significant bit of byte 7 fro m the scratchpad, the polyno mial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC fro m the DS18B20 must be shifted into the circuit. At this po int, if the re-calculated CRC was correct, the shift register will contain all 0s. Addit io nal information about the Maxim 1-Wire cyclic redundancy check
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DS18B20

is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products. Figure 9. CRC Generator
INPU T

XOR (MSB)

XOR (LSB)

XOR

1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18B20 is always a slave. When there is only one slave on the bus, the system is referred to as a "single-drop" system; the system is "mult idrop" if there are mult iple slaves on the bus. All data and commands are transmitted least significant bit first over the 1-Wire bus. The fo llowing discussio n of the 1-Wire bus system is broken down into three topics: hardware configuration, transact ion sequence, and 1-Wire signaling (signal t ypes and timing).

HARDWARE CONFIGURATION
The 1-Wire bus has by definit io n only a single data line. Each device (master or slave) interfaces to the data line via an open-drain or 3-state port. This allows each device to "release" the data line when the device is not transmitt ing data so the bus is available for use by another device. The 1-Wire port of the DS18B20 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 10. The 1-Wire bus requires an external pullup resis tor of approximately 5k ; thus, the idle state 1-Wire bus is high. If for any reason a transact ion needs to be suspended, the bus MUST be left in state if the transact ion is to resume. Infinite recovery time can occur between bits so long as the bus is in the inact ive (high) state during the recovery period. If the bus is held low for more than all co mponents on the bus will be reset. Figure 10. Hardware Configuration
V
PU

for the the idle 1-Wire 480 s,

DS18B20 1-Wire PORT
4.7k Rx 1-Wire BUS DQ PIN Rx

TYP Tx Rx = RECEIVE Tx = TRANSMIT

TX 100 MOSFET

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DS18B20

TRANSACTION SEQUENCE
The transact ion sequence for accessing the DS18B20 is as fo llows: Step 1. Init ialization Step 2. ROM Co mmand (fo llowed by any required data exchange) Step 3. DS18B20 Function Co mmand (fo llowed by any required data exchange) It is very important to fo llow this sequence every time the DS18B20 is accessed, as the DS18B20 will not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search ROM [F0h] and Alarm Search [ECh] commands. After issuing eit her of these ROM co mmands, the master must return to Step 1 in the sequence.

INITIALIZATION
All transact ions on the 1-Wire bus begin wit h an init ializat ion sequence. consists of a reset pulse transmitted by the bus master fo llowed by presence slave(s). The presence pulse lets the bus master know that slave devices (such bus and are ready to operate. Timing for the reset and presence pulses is deta sect ion. The init ialization sequenc e pulse(s) transmitted by the as the DS18B20) are on the iled in the 1-Wire Signaling

ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM co mmand. These co mmand s operate on the unique 64-bit ROM codes of each slave device and allow the master to single out a specific device if many are present on the 1-Wire bus. These co mmands also allow the master to determine how many and what types of devices are present on the bus or if any device has experienced an alar m condit ion. There are five ROM co mmands, and each co mmand is 8 bits lo ng. The master device must issue an appropriate ROM co mmand before issuing a DS18B20 funct ion command. A flowchart for operation of the ROM commands is shown in Figure 11. SEARCH ROM [F0h] When a system is init ially powered up, the master must ident ify the ROM codes o f all slave devices on the bus, which allows the master to determine the number of slaves and their device t ypes. The master learns the ROM codes through a process of elimination that requires the master to perform a Search ROM cycle (i.e., Search ROM co mmand fo llowed by data exchange) as many t imes as necessary to ident ify all of the slave devices. If there is only one slave on the bus, the simpler Read ROM co mmand (see below) can be used in place of the Search ROM process. For a detailed explanat ion of the Search ROM procedure, refer to the iButton® Book of Standards at www. maxim-ic.co m/ibuttonbook. After ever y Search ROM cycle, the bus master must return to Step 1 (Init ializat ion) in the transaction sequence. READ ROM [33h] This co mmand can only be used when there is one slave on the bus. It allows the bus master to read the slave's 64-bit ROM code without using the Search ROM procedure. If this co mmand is used when there is more than one slave present on the bus, a data collisio n will occur when all the slaves attempt to respond at the same time. MATCH ROM [55h] The match ROM command fo llowed by a 64-bit ROM code sequence allows the bus master to address a specific slave device on a mult idrop or single-drop bus. Only the slave that exact ly matches the 64-bit ROM code sequence will respond to the funct ion command issued by the master; all other slaves on the bus will wait for a reset pulse.
iButton is a r egis ter ed trademark of Max im Integrated Pr oducts, Inc.

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DS18B20

SKIP ROM [CCh] The master can use this co mmand to address all devices on the bus simultaneously without sending out any ROM code informat ion. For example, the master can make all DS18B20s on the bus perfor m simultaneous temperature conversio ns by issuing a Skip ROM co mmand fo llowed by a Convert T [44h] command. Note that the Read Scratchpad [BEh] co mmand can fo llow the Skip ROM co mmand only if there is a single slave device on the bus. In this case, time is saved by allowing the master to read fro m the slave without sending the device's 64-bit ROM code. A Skip ROM co mmand fo llowed by a Read Scratchpad command will cause a data co llisio n on the bus if there is more than one slave since mult iple devices will attempt to transmit data simultaneously. ALARM SEARCH [ECh] The operation of this co mmand is ident ical to the operation of the Search ROM command except that only slaves wit h a set alarm flag will respond. This co mmand allows the master device to determine if any DS18B20s experienced an alarm condit ion during the mo st recent temperature conversio n. After every Alarm Search cycle (i.e., Alarm Search co mmand fo llowed by data exchange), the bus master must return to Step 1 (Init ializat ion) in the transact ion sequence. See the Operation--Alarm Signaling section for an explanat ion of alarm flag operation.

DS18B20 FUNCTION COMMANDS
After the bus master has used a ROM co mmand to address the DS18B20 with which it wishes to communicate, the master can issue one of the DS18B20 function co mmands. These commands allo w the master to write to and read fro m the DS18B20's scratchpad memory, init iate temperature conversio ns and determine the power supply mode. The DS18B20 funct ion co mmands, which are described below, are summarized in Table 3 and illustrated by the flowchart in Figure 12. CONVERT T [44h] This co mmand init iates a single temperature conversion. Following the conversio n, the result ing therma l data is stored in the 2-byte temperature register in the scratchpad memory and the DS18B20 returns to its low-power idle state. If the device is being used in parasite power mode, within 10 s (max) after this command is issued the master must enable a strong pullup on the 1-Wire bus for the duration of the conversio n (tCONV) as described in the Powering the DS18B20 section. If the DS18B20 is powered by a n external supply, the master can issue read t ime slo ts after the Convert T command and the DS18B20 will respond by transmitt ing a 0 while the temperature conversio n is in progress and a 1 when the conversion is done. In parasite power mode this notification technique cannot be used since the bus is pulled high by the strong pullup during the conversio n. WRITE SCRATCHPAD [4Eh] This co mmand allo ws the master to write is written into the TH register (byte 2 of (byte 3), and the third byte is written int least significant bit first. All three bytes may be corrupted. 3 bytes of data to the DS18B20's scratchpad. The fir the scratchpad), the second byte is written into the o the configuration register (byte 4). Data must be MUST be written before the master issues a reset, st data byte TL register transmitted or the data

READ SCRATCHPAD [BEh] This command allows the master to read the contents o f the scratchpad. The data transfer starts with the least significant bit of byte 0 and cont inues through the scratchpad unt il the 9th byte (byte 8 ­ CRC) is read. The master may issue a reset to terminate reading at any t ime if o nly part of the scratchpad data is needed.

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COPY SCRATCHPAD [48h] This co mmand copies the contents of the scratchpad TH, TL and configurat ion registers (bytes 2, 3 and 4) to EEPROM. If the device is being used in parasite power mode, within 10 s (max) after this co mmand is issued the master must enable a strong pullup on the 1-Wire bus for at least 10ms as described in the Powering the DS18B20 section. RECALL E2 [B8h] This co mmand recalls the alarm trigger values (TH and TL) and configurat ion data from EEPROM and places the data in bytes 2, 3, and 4, respect ively, in the scratchpad memory. The master device can issue read time slots fo llowing the Recall E2 command and the DS18B20 will indicate the status of the recall by transmitt ing 0 while the recall is in progress and 1 when the recall is done. The recall operation happens automat ically at power-up, so valid data is available in the scratchpad as soon as power is applied to the device. READ POWER SUPPLY [B4h] The master device issues this command fo llowed by a read time slot to determine if any DS18B20s on the bus are using parasite power. During the read time slot, parasite powered DS18B20s will pull the bus low, and externally powered DS18B20s will let the bus remain high. See the Powering the DS18B20 sect ion for usage informat ion for this command. Table 3. DS18B20 Function Command Set 1-Wire BUS COMMAND DESCRIPTION PROTOCOL ACTIVITYAFTER COMMAND IS ISSUED TEMPERATURE CONVERSION COMMANDS Convert T Init iates temperature DS18B20 transmits conversio n. conversio n status to master 44h (not applicable for parasitepowered DS18B20s). MEMORY COMMANDS Read Reads the ent ire scratchpad DS18B20 transmits up to 9 BEh Scratchpad including the CRC byt e. data bytes to master. Write Writes data into scratchpad Master transmit s 3 data bytes Scratchpad bytes 2, 3, and 4 (TH, TL, to DS18B20. 4Eh and configurat ion registers). Copy Copies TH, TL, and None Scratchpad configuration register data 48h fro m the scratchpad to EEPROM. 2 Recalls TH, TL, and DS18B20 transmits recall Recall E configuration register data status to master. B8h fro m EEPROM to the scratchpad. Read Power Signals DS18B20 power DS18B20 transmits supply B4h Supply supply mode to the master. status to master.
Note 1: Note 2: Note 3:

NOTES

1

2 3

1

For parasite-powered DS18B20s, the master must enable a strong pullup on the 1-Wire bus during temperature conversions and copies from the scratchpad to EEPROM. No other bus activity may take place during this time. The master can interrupt the transmission of data at any time by issuing a reset. All three bytes must be written before a reset is issued. 12 of 22


DS18B20

Figure 11. ROM Commands Flowchart
Initialization Sequence
MASTER TX RESET PULSE

DS18B20 TX PRESENCE PULSE

MASTER TX ROM COMMAND

33h READ ROM COMMAND Y

N

55h MATCH ROM COMMAND Y MASTER TX BIT 0

N

F0h SEARCH ROM COMMAND Y

N

ECh N ALARM SEARCH COMMAND Y

CCh SKIP ROM COMMAND Y

N

DS18B20 TX BIT 0 DS18B20 TX BIT 0 DS18B20 TX FAMILY C ODE 1 BYTE BIT 0 MATCH? DS18B20 TX SERIAL NUMBER 6 BYTES Y N N MASTER TX BIT 0

DS18B20 TX BIT 0 DS18B20 TX BIT 0 MASTER TX BIT 0

BIT 0 MATCH? Y

DEVICE(S) WITH ALARM FLAG SET? Y

N

DS18B20 TX BIT 1 DS18B20 TX CRC BYTE MASTER TX BIT 1 DS18B20 TX BIT 1 MASTER TX BIT 1

BIT 1 MATCH?

N

N

BIT 1 MATCH? Y

Y

DS18B20 TX BIT 63 MASTER TX BIT 63 DS18B20 TX BIT 63 MASTER TX BIT 63

N BIT 63 MATCH?

N BIT 63 MATCH? Y

Y

MASTER TX FUNC TION COMMAND (FIGURE 12)

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Figure 12. DS18B20 Function Commands Flowchart
MASTER TX FUNC TION COMMAND 44h CONVERT TEMPERATURE ? Y N 48h COPY SCRATCHPAD ? Y N

N

PARASITE POW ER ?

Y

N

PARASITE POW ER ?

Y

DS18B20 BEGINS CONVERSION

MASTER ENABLES STRON G PULLUP ON DQ

MASTER ENABLES STRON G PULL-UP ON DQ

DEVICE CONVERTIN G TEMPERATURE ? Y

DS18B20 CONVERTS TEMPERATURE N

DATA COP IED FROM SCRATCHPAD TO EEPROM COPY IN PROGRESS ? Y N

MASTER DISABLES STRON G PULLUP

MASTER DISABLES STRON G PULLUP

MASTER RX "0s"

MASTER RX "1s"

MASTER RX "0s"

MASTER RX "1s"

N

B4h READ POW ER SUPPLY ? Y

N

B8h RECALL E ? Y

2

N

BEh READ SCRATCHPAD ? Y

N

4Eh WRITE SCRATCHPAD ? Y MASTER TX TH BYTE TO SCRATCHPAD

N

PARASITE POW ERED ?

Y MASTER BEGINS DATA 2 RECALL FROM E PROM

MASTER RX DATA BYTE FROM SCRATCHPAD

MASTER TX TL BYTE TO SCRATCHPAD MASTER RX "1s" MASTER RX "0s" DEVICE BUSY RECALLING DATA ? Y N MASTER TX RESE T ? N Y

MASTER TX CONFIG. BYTE TO SCRATCHPAD

N

HAVE 8 BYTES BEEN READ ? Y

MASTER RX "0s"

MASTER RX "1s"

MASTER RX SCRATCHPAD CRC BYTE

RETURN TO IN ITIALIZA TION SEQUENCE (FIGURE 11) FOR NEXT TRANSACTION

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1-WIRE SIGNALING
The DS18B20 uses a strict 1-Wire co mmunicat ion protocol to ensure data integrit y. Several signal types are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. The bus master init iates all these signals, with the exception of the presence pulse.

INITIALIZATION PROCEDURE--RESET AND PRESENCE PULSES
All communication wit h the DS18B20 begins wit h an init ializat ion sequence that consists of a reset pulse fro m the master fo llowed by a presence pulse from the DS18B20. This is illustrated in Figure 13. Whe n the DS18B20 sends the presence pulse in response to the reset, it is indicat ing to the master that it is o n the bus and ready to operate. During the init ializat ion sequence the bus master transmits (TX) the reset pulse by pulling the 1-Wire bu s low for a minimum of 480 s. The bus master then releases the bus and goes into receive mode (RX). When the bus is released, the 5k pullup resistor pulls the 1-Wire bus high. When the DS18B20 detects this rising edge, it waits 15 s to 60 s and then transmit s a presence pulse by pulling the 1-Wire bus low for 60 s to 240 s. Figure 13. Initialization Timing
M ASTER TX RESET PULSE 480 s minimum DS 18B20 wait s 15- 60 s M ASTER RX 480 s minimum DS18B20 TX presence pulse 60- 240 s

VPU 1-WIR E BUS GND

LINE T YPE LEG END Bus master pulling low DS18B20 pulling low R esistor pullup

READ/WRITE TIME SLOTS
The bus master writes data to the DS18B20 during write t ime slots and reads data from the DS18B20 during read time slots. One bit of data is transmitted over the 1-Wire bus per time slot.

WRITE TIME SLOTS
There are two types of write time slots: "Write 1" time slots and "Write 0" time slots. The uses a Write 1 t ime slot to write a logic 1 to the DS18B20 and a Write 0 t ime slot to write a lo DS18B20. All write t ime slots must be a minimum of 60 s in durat ion with a minimum o f a 1 time between individual write slots. Both types of write time slots are init iated by the master 1-Wire bus low (see Figure 14). To generate a Write 1 t ime bus wit hin 15 s. When the Write 0 time slot, after pull the duration of the time slot bus master gic 0 to the s recover y pulling the

slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wire bus is released, the 5k pullup resistor will pull the bus high. To generate a ing the 1-Wire bus lo w, the bus master must continue to hold the bus low for (at least 60 s).
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DS18B20

The DS18B20 samples the 1-Wire bus during a window that lasts fro m 15 s to 60 s after the master init iates the write time slot. If the bus is high during the sampling window, a 1 is written to the DS18B20. If the line is low, a 0 is written to the DS18B20. Figure 14. Read/Write Time Slot Timing Diagram
START OF SLOT START OF SLOT

M ASTER WRITE "0" SLOT 60 s < TX "0" < 120 s VPU 1-WIR E BUS GND DS 18B20 Samples
MIN T YP MAX

M ASTER WRITE "1" SLOT 1 s REC

<

>1 s

DS18B20 Samples
MIN T YP MAX

15 s

15 s

30 s

15 s

15 s

30 s

M ASTER READ "0" SLOT VPU 1-WIR E BUS GND M aster samples >1 s 15 s 45 s 15 s >1 s

M ASTER READ "1" SLOT 1 s REC

<

M aster samples

LINE T YPE LEG END Bus master pulling low R esistor pullup DS18B20 pulling low

READ TIME SLOTS
The DS18B20 can only transmit data to the master when the master issues read t ime slots. Therefore, the master must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power Supply [B4h] co mmand, so that the DS18B20 can provide the requested data. In addition, the master can generate read time slots after issuing Convert T [44h] or Recall E2 [B8h] co mmands to find out the status of the operation as explained in the DS18B20 Function Commands section. All read t ime slots must be a minimum o f 60 s in durat ion wit h a minimum o f a 1 s recovery time between slots. A read time slot is init iated by the master device pulling the 1-Wire bus low for a minimum of 1 s and then releasing the bus (see Figure 14). After the master init iates the read t ime slot, the DS18B20 will begin transmitting a 1 or 0 on bus. The DS18B20 transmits a 1 by leaving the bus hig h and transmits a 0 by pulling the bus low. When transmitt ing a 0, the DS18B20 will release the bus by the end o f the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output
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DS18B20

data from the DS18B20 is valid for 15 s after the falling edge that init iated the read time slot. Therefore, the master must release the bus and then sample the bus state within 15 s fro m the start of the slot. Figure 15 illustrates that the sum o f TINIT, TRC, and TSAMPLE must be less than 15 s for a read time slot. Figure 16 shows that system t iming margin is maximized by keeping TINIT and TRC as short as possible and by locat ing the master sample time during read time slots towards the end of the 15 s period. Figure 15. Detailed Master Read 1 Timing
VPU 1-WIR E BUS GND T
INT

VIH of M aster

>1 s

T

RC

M aster samples

15 s

Figure 16. Recommended Master Read 1 Timing
VPU 1-WIR E BUS GND TINT = TRC = small small 15 s M aster samples VIH of M aster

LINE T YPE LEG END Bus master pulling low R esistor pullup

RELATED APPLICATION NOTES
The fo llowing application notes can be applied to the DS18B20 and are available on our website at www.maxim-ic.co m. Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products Application Note 122: Using Dallas' 1-Wire ICs in 1-Cell Li-Ion Battery Packs with Low-Side N-Channel Safety FETs Master Application Note 126: 1-Wire Communication Through Software Application Note 162: Interfacing the DS18x20/DS1822 1-Wire Temperature Sensor in a Microcontroller Environment Application Note 208: Curve Fitting the Error of a Bandgap-Based Digital Temperature Sensor Application Note 2420: 1-Wire Communication with a Microchip PICmicro Microcontroller Application Note 3754: Single-Wire Serial Bus Carries Isolated Power and Data Sample 1-Wire subroutines that can be used in conjunct ion wit h Application Note 74: Reading and Writing iButtons via Serial Interfaces can be downloaded fro m the Maxim website.
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DS18B20 OPERATION EXAMPLE 1
In this example there are mult iple DS18B20s on the bus and they are using parasite power. The bus master init iates a temperature conversion in a specific DS18B20 and then reads its scratchpad and recalculates the CRC to verify the data.
MASTER MODE Tx Rx Tx Tx Tx Tx Tx Rx Tx Tx Tx Rx DATA (LSB FIRST) Reset Presence 55h 64-bit ROM code 44h DQ line held high by strong pullup Reset Presence 55h 64-bit ROM code BEh 9 data bytes COMMENTS Master issues reset pulse. DS18B20s respond with presence pulse. Master issues Match ROM comma nd. Master sends DS18B20 ROM code. Master issues Convert T comma nd. Master applies strong pullup to DQ for the duration of the conversion (tCONV). Master issues reset pulse. DS18B20s respond with presence pulse. Master issues Match ROM comma nd. Master sends DS18B20 ROM code. Master issues Read Scratchpad comma nd. Master reads entire scratchpad including CRC. The ma ster then recalculates the CRC of the first eight data bytes from the scratchpad and compares the calculated CRC with the rea d CRC (byte 9). If they match, the master continues; if not, the read operation is repeated.

DS18B20 OPERATION EXAMPLE 2
In this example there is only one DS18B20 on the bus and it is using parasite power. The master writes to the TH, TL, and configuration registers in the DS18B20 scratchpad and then reads the scratchpad and recalculates the CRC to verify the data. The master then copies the scratchpad contents to EEPROM.
MASTER MODE Tx Rx Tx Tx Tx Tx Rx Tx Tx Rx Tx Rx Tx Tx Tx DATA (LSB FIRST) COMMENTS Reset Master issues reset pulse. Presence DS18B20 responds with presence pulse. CCh Master issues Skip ROM comma nd. 4Eh Master issues Write Scratchpad comma nd. 3 data bytes Master sends three data bytes to scratchpad (TH, TL, and config). Reset Master issues reset pulse. Presence DS18B20 responds with presence pulse. CCh Master issues Skip ROM comma nd. BEh Master issues Read Scratchpad comma nd. Master reads entire scratchpad including CRC. The ma ster then recalculates the CRC of the first eight data bytes from the scratchpad and compares the calculated CRC with the rea d CRC 9 data bytes (byte 9). If they match, the master continues; if not, the read operation is repeated. Reset Master issues reset pulse. Presence DS18B20 responds with presence pulse. CCh Master issues Skip ROM comma nd. 48h Master issues Copy Scratchpad comma nd. DQ line held high by Master applies strong pullup to DQ for at least 10ms while copy strong pullup operation is in progress.

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DS18B20

ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relat ive to Ground ..................................................................-0.5V to +6.0V Operating Temperature Range ....................................................................................... -55 C to +125 C Storage Temperature Range ........................................................................................... -55 C to +125 C Solder Temperature ..................................................... Refer to the IPC/JEDEC J-STD-020 Specificat ion. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Vo ltage Pullup Supply Voltage Thermo meter Error Input Logic-Low Input Logic-High Sink Current Standby Current Act ive Current DQ Input Current Drift SYMBOL VDD VPU t
ERR

(-55°C to +125°C; VDD=3.0V to 5.5V)
TYP MAX +5.5 +5.5 VDD ±0.5 ±2 +0.8 The lower of 5.5 or VDD + 0.3 1000 1.5 UNITS V V °C V V mA nA mA A °C NOTES 1 1,2 3 1,4,5 1, 6 1 7,8 9 10 11

VIL VIH

CONDITIONS MIN Local Power +3.0 Parasite Power +3.0 Local Power +3.0 -10°C to +85°C -55°C to +125°C -0.3
Local Power

+2.2 +3.0 4.0 750 1 5 ±0.2

Parasite Power IL IDDS IDD IDQ VI/O = 0.4V VDD = 5V

NOTES:
1) All vo ltages are referenced to ground. 2) The Pullup Supply Voltage specificat ion assumes that the pullup device is ideal, and therefore the high level o f the pullup is equal to VPU. In order to meet the VIH spec of the DS18B20, the actual supply rail for the strong pullup transistor must include margin for the vo ltage drop across the transistor when it is turned on; thus: VPU_ACT UAL = VPU_IDEAL + VTRANSISTOR. 3) See typical performance curve in Figure 17. 4) Logic-low vo ltages are specified at a sink current of 4mA. 5) To guarantee a presence pulse under low vo ltage parasite power condit ions, VILMAX may have to be reduced to as low as 0.5V. 6) Logic-high vo ltages are specified at a source current of 1mA. 7) Standby current specified up to +70 C. Standby current typically is 3 A at +125 C. 8) To minimize IDDS, DQ should be wit hin the fo llowing ranges: GND DQ GND + 0.3V or VDD ­ 0.3V DQ VDD. 9) Act ive current refers to supply current during act ive temperature conversio ns or EEPROM writes. 10) DQ line is high ("high-Z" state). 11) Drift data is based on a 1000-hour stress test at +125°C wit h VDD = 5.5V.

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AC ELECTRICAL CHARACTERISTICS--NV MEMORY (-55°C to +100°C; V
PARAMETER NV Write Cycle Time EEPROM Writes EEPROM Data Retention SYMBOL tWR NEEWR tEEDR CONDITIONS -55°C to +55°C -55°C to +55°C MIN 50k 10 TYP 2

DD

= 3.0V to 5.5V)
UNITS ms writes years

MAX 10

AC ELECTRICAL CHARACTERISTICS
PARAMETER Temperature Conversio n Time Time to Strong Pullup On Time Slot Recovery Time Write 0 Low Time Write 1 Low Time Read Data Valid Reset Time High Reset Time Low Presence-Detect High Presence-Detect Low Capacitance SYMBOL t
CONV

(-55°C to +125°C; V

DD

= 3.0V to 5.5V)
UNITS ms s s s s s s s s s s pF 1 1 1 1 1 1 1,2 1 1 NOTES 1

t

SPON

tSLOT tREC tLOW0 tLOW1 tRDV tRSTH tRSTL tPDHIGH tPDLOW CIN/OUT

CONDITIONS MIN TYP 9-bit resolut ion 10-bit resolut ion 11-bit resolut ion 12-bit resolut ion Start Convert T Command Issued 60 1 60 1 480 480 15 60

MAX 93.75 187.5 375 750 10 120 120 15 15

60 240 25

NOTES:
1) See the timing diagrams in Figure 18. 2) Under parasite power, if tRSTL > 960 s, a power-on reset may occur. Figure 17. Typical Performance Curve
DS18B20 Typical Error Curve 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5

Thermometer Error (°C)

+3s Error

0

10

20

30

40

50

60

70

Mean Error -3s Error Temperature (°C)

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Figure 18. Timing Diagrams

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DS18B20

REVISION HISTORY
REVISION DATE 030107 DESCRIPTION In the Absolute Maximum Ratings section, removed the reflow oven temperature value o f +220 C. Reference to JEDEC specificat ion for reflow remains. In the Operation--Alarm Signaling section, added "or equal to" in the desciption for a TH alarm condit io n In the Memory section, removed incorrect text describing memory. In the Configuration Register section, removed incorrect text describing configuration register. In the Ordering Information table, added TO-92 straight-lead packages and included a note that the TO-92 package in tape and reel can be ordered with either formed or straight leads. PAGES CHANGED 19 5 7 8 2

101207

042208

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

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