Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.apo.nmsu.edu/arc35m/Instruments/ARCES/ccd_77.pdf Дата изменения: Fri Feb 10 20:39:19 2012 Дата индексирования: Mon Oct 1 20:01:49 2012 Кодировка: Поисковые слова: apollo 11

CCD77-00 Back Illuminated High Performance IMO Device

FEATURES
* * * * * * * *

512 by 512 Image Format Image Area 12.3 x 12.3 mm Full-Frame Operation 24 mm Square Pixels Back Illuminated for High Quantum Efficiency Low Noise Output Amplifiers 100% Active Area Inverted Mode Operation

APPLICATIONS
* * * *

Spectroscopy Scientific Imaging Star Tracking Medical Imaging

INTRODUCTION
The CCD77 family of sensors are full-frame devices with readout registers above and below the image section. The top register, image section and bottom register are designated A, B and C respectively. Each register has a single output at one end and a charge injection structure at the other end for test purposes. Standard three-phase clocking and buried channel charge transfer are employed. The image section of the device operates in inverted mode for minimum dark current. To maximise the dynamic range, the CCD is manufactured without anti-blooming structures. The e2v technologies back thinning process ensures high quantum efficiency over a wide range of wavelengths. Several different anti-reflection coatings are available to suit a range of applications. Designers are advised to consult e2v technologies should they be considering using CCD sensors in abnormal environments or if they require customised packaging.

TYPICAL PERFORMANCE
Maximum readout frequency Output responsivity . . Peak signal . . . . . Dynamic range (at 20 kHz) Spectral range . . . . Readout noise (at 20 kHz) . . . . . . . . . . . . . . . . . ....7 MHz . . . . 2.5 mV/e7 . . . 300 ke7/pixel *100 000:1 200 ­ 1060 nm . . . . 3.0 e7 rms

GENERAL DATA
Format
Image area . . . . . Active pixels (H) . . . (V) ... Pixel size . . . . . . Number of output amplifiers . . . . . . . . . . . . . 12.3 x 12.3 . . . 512 . . . 512 . . 24 x 24 mm

mm 2

..........

15 additional pixels are provided for over-scanning purposes in each register.

Package
Package size . . Number of pins . Inter-pin spacing Inter-row spacing Window material Type . . . . Weight (approx, no ... ... ... ... ... ... window) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.6 x 29.9 .. 24 . . . 2.54 .. 22.86 . . removable . ceramic DIL ...6 mm mm mm glass array g

e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU, UK Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492 e-mail: enquiries@e2v.com Internet: www.e2v.com Holding Company: e2v technologies plc e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148 e-mail: enquiries@e2vtechnologies-na.com

# e2v technologies (uk) limited 2006

A1A-100034 Issue 4, March 2006
411/9572


PERFORMANCE
Min Peak charge storage (see note 1) Peak output voltage (no binning) Dark signal at 293 K (see notes 2 and 3) Dynamic range (see note 4) Charge transfer efficiency (see note 5): parallel serial Output amplifier responsivity (see note 3) Readout noise at 253 K (see notes 3 and 6) Maximum readout frequency (see note 7) Dark signal non-uniformity at 293 K (std. deviation) (see notes 3 and 8) Output node capacity 300k ­ ­ ­ ­ ­ 1.8 ­ ­ ­ ­ Typical 350k 875 700 100 000:1 99.9999 99.9993 2.5 3.0 1000 175 600k Max ­ ­ 1500 ­ ­ ­ 3.5 5.0 7000 375 ­
7

e7/pixel mV e7/pixel/s

% % mV/e
7

rms e /pixel kHz e7/pixel/s electrons

Spectral Response (at 253 K)
Wavelength (nm) 350 400 500 650 900 Minimum Response (QE) (all Basic Process) Midband Coated 15 40 85 85 30 Broadband Coated 25 55 75 75 30 Uncoated 10 25 55 50 30 Maximum Response Non-uniformity (1s) 5 3 3 3 5 % % % % %

The uncoated process is suitable for soft X-ray and EUV applications.

NOTES
1. Signal level at which resolution begins to degrade. 2. Measured between 253 and 293 K and VSS +9.5 V typically. Dark signal at any temperature T (kelvin) may be estimated from: Qd/Qd0 = 1.14 x 106T3e79080/T where Qd0 is the dark signal at T = 293 K (20 8C). 3. Test carried out at e2v technologies on all sensors. 4. Dynamic range is the ratio of full-well capacity to readout noise measured at 253 K and 20 kHz readout speed. 5. CCD characterisation measurements made using charge generated by X-ray photons of known energy. 6. Measured using a dual-slope integrator technique (i.e. correlated double sampling) with a 20 ms integration period. 7. Readout at speeds in excess of 7 MHz can be achieved but performance to the parameters given cannot be guaranteed. 8. Measured between 253 and 293 K, excluding white defects.

White spots

White column Black column

Are counted when they have a generation rate 50 times the specified maximum dark signal generation rate (measured between 253 and 293 K). The typical temperature dependence of white spot defects is different from that of the average dark signal and is given by: Qd/Qd0 = 122T3e76400/T A column which contains at least 9 white defects. A column which contains at least 9 black defects. 0 0 0 2 20 20 1 2 0 5 30 30 2 6 1 10 100 60

GRADE Column defects: black or slipped white Traps 4200 e7 White spots Black spots Grade 5

BLEMISH SPECIFICATION
Pixels where charge is temporarily held. Traps are counted if they have a capacity greater than 200 e7 at 253 K. Slipped columns Are counted if they have an amplitude greater than 200 e7. Black spots Are counted when they have a signal level of less than 80% of the local mean at a signal level of approximately half full-well. Traps

Devices which are fully functioning, with image quality below that of grade 2, and which may not meet all other performance parameters.

Note The effect of temperature on defects is that traps will be observed less at higher temperatures but more may appear below 253 K. The amplitude of white spots and columns will decrease rapidly with temperature.

100034, page 2

# e2v technologies


TYPICAL OUTPUT CIRCUIT NOISE
8026

18 16 14 rms)
--

12 10 8 6 4 2 0 10k FREQUENCY (Hz)

NOISE EQUIVALENT SIGNAL (e

50k

100k

500k

1M

5M

TYPICAL SPECTRAL RESPONSE
100
8012

90

BASIC MIDBAND COATED

80 BASIC BROADBAND COATED 70

60

BASIC UNCOATED

50

40

30

QUANTUM EFFICIENCY (%)

20

10

0 200

300

400

500

600

700

800

900

1000

1100

WAVELENGTH (nm)

# e2v technologies

100034, page 3


TYPICAL VARIATION OF DARK SIGNAL WITH SUBSTRATE VOLTAGE AT 20 8C
10
6

8035

10

5

TYPICAL RANGE 10
4

DARK SIGNAL (e7/pixel/s)

10

3

10

2

0 1 2 SUBSTRATE VOLTAGE (V)

3

4

5

6

7

8

9

10

11

12

TYPICAL VARIATION OF DARK SIGNAL WITH TEMPERATURE (V
10
4

SS

= +9.5 V)

8034

10

3

10

2

10 DARK SIGNAL (e7/pixel/s)

1

10

71

10

72

740 720 PACKAGE TEMPERATURE (8C)

0

20

40

100034, page 4

# e2v technologies


DEVICE SCHEMATIC
8033

IDA

1

24 OSA

B13

2

23 B11

TGA

3

A REGISTER

512 + 15 ELEMENTS

22 TGC

A13

4

21 B12

OG

5

20 IG

6 IMAGE (B) SECTION 512 x 512 PIXELS SS 7

19

18 SS

1R

8

17 C13

A12

9

16 C12

A11 10

C REGISTER

512 + 15 ELEMENTS

15 C11

OD 11

14 RD

OSC 12

13 IDC

# e2v technologies

100034, page 5


CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS
CLOCK LOW TYPICAL 0 0 0 1 n/a 0 n/a 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 8 10 10 10 15 8 8 8 8 8 8 8 8 27 10 10 8 1 PULSE AMPLITUDE OR DC LEVEL (V) Min Typical Max see note 9 12 12 10 3 ­ 9.5 12 10 10 29 see note 10 see note 9 17 10 10 10 9.5 ­ 10 12 12 12 see note 10 15 15 15 15 19 15 15 15 11 11 15 15 15 32 15 15 15 5 MAXIMUM RATINGS with respect to VSS +20 V +20 V +20 V +20 V +20 V ­ ­ +20 V +20 V +20 V 70.3 to +35 V 70.3 to +35 V 70.3 to +25 V 70.3 to +25 V +20 V +20 V +20 V ­ ­ +20 V +20 V +20 V +20 V +20 V

PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

REF IDA B13 TGA A1 3 OG ­ SS 1R A1 2 A1 1 OD OSC IDC RD C11 C12 C13 SS ­ IG B12 TGC B11 OSA

DESCRIPTION Input diode A Image clock Transfer gate A Register clock A Output gate (A and C) No connection Substrate Reset (A and C) Register clock A Register clock A Output drain (A and C) Output source C Input diode C Reset drain (A and C) Register clock C Register clock C Register clock C Substrate No connection Input gate Image clock Transfer gate C Image clock Output source A

Maximum voltages between pairs of pin 11 (OD) to pin 24 (OSA) . pin 11 (OD) to pin 12 (OSC) . . Maximum output transistor current

pins: . . . . . +15 V . . . . . +15 V . . . . . . 10 mA

NOTES
9. For normal operation, the input gate should be set to 0 V and the input diode to approx. 22 V. To inject charge for test purposes, the input gate should be pulsed high during the period when A11 is high and the input diode should be adjusted for the required charge injection. Typical uses for such charge injection include assessing charge transfer efficiency, and the measurement of output responsivity using the reset drain current method. 10. 3 to 5 V below OD. Connect to ground using a 5 mA current source or appropriate load resistor (typically 5 kO). 11. All devices will operate at the typical values given. However, some adjustment within the minimum to maximum range may be required to optimise performance for critical applications. It should be noted that conditions for optimum performance may differ from device to device. 12. With the B1 connections shown, charge is transferred to the top register, A. In order to transfer charge to the bottom register, B11 and B12 connections should be reversed. Refer to the waveform diagram.

100034, page 6

# e2v technologies


ELECTRICAL INTERFACE CHARACTERISTICS
An approximate equivalent circuit to represent the load presented by the image section or output registers is shown below.
8028

11

R

1

COV C C
3 1

C

OV

C

2

SS R
3

R

2

13

COV

12

Typical Electrode Capacitances (measured at mid-clock level)
I1/I1 interphase (COV) I11/SS and I12/SS (C I13/SS (C3) . . . . R1/R1 interphase . R1/SS . . . . . 1R/SS . . . . . . , 1 . . . . . C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 . . 3.5 . 12 . 30 . 60 . 20 nF nF nF pF pF pF

Typical Electrode Series Resistance
I11 and I12 (R1, R2) . . . I13 (R3) . . . . . . . R11, 2, 3 . . . . . . . Output amplifier impedance at typical operating conditions ....... ....... ....... ....... 20 14 20 400 O O O O

# e2v technologies

100034, page 7


DETAIL OF LINE TRANSFER
8030

Towards A B11 t2 B12 t1 B13 & TGA t3 t
2

Towards C B12 t3 B11

B13 & TGC

TGC

TGA

t

dri

t

dir

A11

C11

A12

C12

A13

C13

1RA

1RC

Clocking Sequence
During the integration period, all B1 electrodes should be low ­ the IMO implant takes care of charge gathering. For transfer to the A register, use the labelling of waveforms on the left of the diagram. Charge is transferred to the register when B13 and TGA are taken from high to low. For transfer to the C register, use the labelling of waveforms on the right of the diagram. Charge is transferred to the register when B13 and TGC are taken from high to low. If only one register is used, the recommended approach for the unused register is to tie its clocks high and its TG low. Any charge collected in the unused register would then spill over OG and drain out through RD, thus keeping unwanted charge out of the image section. Continuous clocking of the unused register can be used but may generate extra heat, potentially causing more dark current in the image area.

100034, page 8

# e2v technologies


DETAIL OF OUTPUT CLOCKING
8036

R11 Tr tor

R12

R13 twx 1R OUTPUT VALID OS SIGNAL OUTPUT tdx

RESET FEEDTHROUGH

LINE OUTPUT FORMAT
8031

15 BLANK

512 ACTIVE OUTPUTS

CLOCK TIMING REQUIREMENTS
Symbol t1 t2 t3 tri tfi tdri tdir tlt Tr trr tfr tor twx trx, t tdx Description Image clock overlap/delay Image clock overlap/delay Image clock overlap/delay Image clock pulse rise time (10 to 90%) Image clock pulse fall time (10 to 90%) Post register clocking delay Pre register clocking delay Line transfer/vertical shift time Output register clock cycle period Clock pulse rise time (10 to 90%) Clock pulse fall time (10 to 90%) Clock pulse overlap Reset pulse width Reset pulse rise and fall times Delay time, 1R low to R13 low Min 10.0 0.65 1.1 0.1 tri 1.0 1.65 16.0 140 20 trr 10 20 0.2twx 30 Typical 20.0 1.0 2.0 5 tri 2.0 3.0 32.0 1000 0.1Tr 0.1Tr 0.5trr 0.1Tr 0.5trr 0.5Tr see see see Ti Ti see see see see Max note 13 note 13 note 13 7 2twi 7 2twi note 13 note 13 note 13 note 13 0.3Tr 0.3Tr 0.1Tr 0.3Tr 0.1Tr 0.8Tr ms ms ms ms ms ms ms ms ns ns ns ns ns ns ns

fx

NOTES
13. No maximum other than that set by system constraints on the total readout period.

# e2v technologies

100034, page 9


FUNCTIONAL DIAGRAM
Output A 1
OGA SWA A12 A11 A13

8029

16
A13 A12 A11 A13 A12 A11 A13 TGA TGA B12 B11 B13 B12 B11 B13 A12 A11 A13 A12 A11 A13 A12 A11 A13 A12 A11 A13 TGA B12 B11 B13 B12 B11 B13 TGA B12 B11 B13 B12 B11 B13 TGA B12 B11 B13 B12 B11 B13 TGA B12 B11 B13 B12 B11 B13

527
A12 A11 A13 A12 A11 IGA TGA B12 B11 B13 B12 B11 B13 TGA B12 B11 B13 B12 B11 B13 IDA

ROW 1

B12 B11 B13 B12 B11

Column 1

B13

B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 B13 B12 B11 B13

ROW 256

B12 B11 B13 B12

Column 512

Optical Centreline

ROW 257

B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13

B12 B11 B13 B12 B11 B13 B12 B11 TGC

B12 B11 B13 B12 B11 B13 B12 B11 TGC

B12 B11 B13 B12 B11 B13 B12 B11 TGC

B12 B11 B13 B12 B11 B13 B12 B11 TGC

B12 B11 B13 B12 B11 B13 B12 B11 TGC

B12 B11 B13 B12 B11 B13 B12 B11 TGC

B12 B11 B13 B12 B11 B13 B12 B11 TGC C13 C11 C12 SWC OGC

ROW 512
IDC

B12 B11 TGC

Output C

IGC C11 C12 C13 C11 C12

C13 C11 C12 C13 C11 C12 C13 C11 C12 C13 C11 C12

C13 C11 C12 C13 C11 C12 C13

527

16

1

= Gate with IMO implant

OUTPUT CIRCUIT
11 12 SW OG 1R RD OD TG (INTERNAL CONNECTION)
8032

OS

OUTPUT

C

n

EXTERNAL LOAD

SUBSTRATE

SS

0V

NOTE
14. SW is joined to 13 in the package.

100034, page 10

# e2v technologies


OUTLINE
(All dimensions without limits are nominal)
A
24 13 8037

IMAGE CENTRE B C

1

12

PIN 1 INDICATOR TEMPORARY COVERGLASS D

IMAGE PLANE E

F

H PITCH

G

Ref A B C D E F G H J K

Millimetres 29.94 + 0.30 22.61 + 0.25 22.86 + 0.25 2.70 + 0.27 1.65 + 0.25 5.6 + 0.5 0.46 + 0.05 2.54 + 0.13 27.94 + 0.13 1.0 + 0.3

K

J

# e2v technologies

100034, page 11


ORDERING INFORMATION
Options include:
* * * *

HANDLING CCD SENSORS
CCD sensors, in common with most high performance MOS IC devices, are static sensitive. In certain cases a discharge of static electricity may destroy or irreversibly degrade the device. Accordingly, full antistatic handling precautions should be taken whenever using a CCD sensor or module. These include:
* * * *

Temporary Glass Window Permanent Window; ask for details UV Coating X-ray Phosphor Coating

Working at a fully grounded workbench Operator wearing a grounded wrist strap All receiving socket pins to be positively grounded Unattended CCDs should not be left out of their conducting foam or socket.

In common with other e2v technologies CCD Sensors, a front illuminated CCD77-00 is available with a fibre-optic window or taper. For further information on the performance of these and other options, please contact e2v technologies.

Evidence of incorrect handling will invalidate the warranty.

HIGH ENERGY RADIATION
Device characteristics will change when subject to ionising radiation. Users planning to operate CCDs in high radiation environments are advised to contact e2v technologies.

TEMPERATURE LIMITS
Min Typical Storage . . . . . . . 153 ­ Operating . . . . . . 153 273 Operation or storage in humid conditions may give the sensor surface on cooling, causing irreversible Maximum device heating/cooling . . . . Max 373 K 323 K rise to ice on damage. . 5 K/min

Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.

100034, page 12

Printed in England

# e2v technologies