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Performance Specification

KAF-6303E

KAF- 6303E 3072 (H) x 2048 (V) Pixel Enhanced Response Full-Frame CCD Image Sensor Performance Specification

Eastman Kodak Company Image Sensor Solutions Rochester, New York 14650-2010

Revision 3.1 March 19, 2004

Eastman Kodak Company - Image Sensor Solutions
www.kodak.com/go/imagers Phone: (585) 722-4385 E-mail: imagers@kodak.com


Performance Specification

KAF-6303E

1.1 1.2 1.3 1.4 1.5 1.6 1.7 2.1 2.2 3.1 3.2 3.3 3.4 4.1 4.2 4.3 5.1 5.2

TABLE OF CONTENTS Features .............................................................................................................................................. 3 Description ......................................................................................................................................... 3 Image Acquisition .............................................................................................................................. 4 Charge Transport ................................................................................................................................ 4 Output Structure ................................................................................................................................. 4 Dark Reference Pixels ....................................................................................................................... 4 Dummy Pixels. ................................................................................................................................... 4 Package Drawing ................................................................................................................................ 5 Pin Description ................................................................................................................................... 6 Absolute Maximum Ratings ............................................................................................................... 7 DC Operating Conditions ................................................................................................................... 8 AC Operating Conditions ................................................................................................................... 9 AC Timing Conditions ....................................................................................................................... 9 Performance Specifications .............................................................................................................. 11 Typical Performance Characteristics Spectral Response ................................................................ 12 Defect Classification ........................................................................................................................ 13 Quality Assurance and Reliability.................................................................................................... 14 Ordering Information ....................................................................................................................... 15

Revision Changes .................................................................................................................................. 16 FIGURES Figure Figure Figure Figure Figure 1 2 3 4 5 Functional Block Diagram Package Diagram Package Pin Designations Recommended Output Structure Load Diagram Timing Diagrams 3 5 6 8 10

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Performance Specification

KAF-6303E
current without compromising charge capacity. The transparent gate results in spectral response increased ten times at 400nm, compared to a front side illuminated standard polysilicon gate technology. The sensitivity is increased 50% over the rest of the visible wavelengths. Total chip size is 29.0 mm x 19.1 mm and is housed in a 26-pin, 0.88" wide DIL ceramic package with 0.1" pin spacing. The sensor consists of 3088 parallel (vertical) CCD shift registers each 2056 elements long. These registers act as both the photosensitive elements and as the transport circuits that allow the image to be sequentially read out of the sensor. The elements of these registers are arranged into a 3072 x 2048 photosensitive array surrounded by a light shielded dark reference of 16 columns and 8 rows. The parallel (vertical) CCD registers transfer the image one line at a time into a single 3100 element (horizontal) CCD shift register. The horizontal register transfers the charge to a single output amplifier. The output amplifier is a two-stage source follower that converts the photo-generated charge to a voltage for each pixel .
4 D a r k lin e s

1.1

Features
6M Pixel Area CCD 3072H x 2048V (9 µm) Pixels Transparent Gate True Two Phase Technology (Enhanced Spectral Response) 27.65mm H x 18.48mm V Photosensitive Area 2-Phase Register Clocking 100% Fill Factor Low Dark Current ( <10pA/cm2 @ 25oC)

1.2

Description

The KAF-6303E is a high performance monochrome area CCD (charge-coupled device) image sensor with 3072H x 2048V photo active pixels designed for a wide range of image sensing applications in the 0.3 nm to 1.0 nm wavelength band. Typical applications include military, scientific, and industrial imaging. A 74dB dynamic range is possible operating at room temperature. The sensor is built with a true two-phase CCD technology. This technology simplifies the support circuits that drive the sensor and reduces the dark

V1

K A F - 6303E
U s a b le A c t i v e I m a g e A r e a 3072 ( H ) x 204 8 ( V ) 9 x 9 µ m p ix e ls 3: 2 a s p ec t r a t i o
Vr d

V2
Gu a r d

R Vd d V out Vs s
Su b Vo g

4 D a r k lin e s

3 0 7 2 A c tiv e P ix e ls /L in e 6 D a rk 10 I n ac t iv e
10 D a r k 2 I n ac t iv e

H1 H2

Figure 1 - Functional Block Diagram
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KAF-6303E
1.5 Output Structure

1.3

Image Acquisition

An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the sensor. These photoninduced electrons are collected locally by the formation of potential wells at each photogate or pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel's capacity is reached, excess electrons will leak into the adjacent pixels within the same column. This is termed blooming. During the integration period, the V1 and V2 register clocks are held at a constant (low) level. See Figure 5. - Timing Diagrams.

Charge presented to the floating diffusion (FD) is converted into a voltage and current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on FD. Once the signal has been sampled by the system electronics, the reset gate (R) is clocked to remove the signal and FD is reset to the potential applied by Vrd. More signal at the floating diffusion reduces the voltage seen at the output pin. In order to activate the output structure, an off-chip load must be added to the Vout pin of the device - see Figure 4.

1.6

Dark Reference Pixels

1.4

Charge Transport

Referring again to Figure 5 - Timing Diagrams, the integrated charge from each photogate is transported to the output using a two step process. Each line (row) of charge is first transported from the vertical CCD's to the horizontal CCD register using the V1 and V2 register clocks. The horizontal CCD is presented a new line on the falling edge of V2 while H1 is held high. The horizontal CCD's then transport each line, pixel by pixel, to the output structure by alternately clocking the H1 and H2 pins in a complementary fashion. On each falling edge of H2 a new charge packet is transferred onto a floating diffusion and sensed by the output amplifier

Surrounding the peripheral of the device is a border of light shielded pixels. This includes 6 leading and 10 trailing pixels on every line excluding dummy pixels. There are also 4 full dark lines at the start of every frame and 4 full dark lines at the end of each frame. Under normal circumstances, these pixels do not respond to light. However, dark reference pixels in close proximity to an active pixel, or the outer bounds of the chip (including the first two lines out), can scavenge signal depending on light intensity and wavelength and therefore will not represent the true dark signal.

1.7

Dummy Pixels

Within the horizontal shift register are 10 leading and 2 trailing additional shift phases that are not associated with a column of pixels from the vertical register. These pixels contain only horizontal shift register dark current signal and do not respond to light. A few leading dummy pixels may scavenge false signal depending on operating conditions.

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KAF-6303E

2.1

Package Drawing

Figure 2 - Package Drawing

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Performance Specification

KAF-6303E

2.2

Pin Description
Pin Symbol Vsub Vout Vdd Vrd R Vss N/C Description Substrate (Ground) Video Output Amplifier Supply Reset Drain Reset Clock Amplifier Supply Return No connection (open pin) Pin 10 11 16, 17, 22, 23 18, 19, 20, 21 24 25 Symbol H1 H2 V1 V2 Vguard Vog Description Horizontal CCD Clock - Phase 1 Horizontal CCD Clock - Phase 2 Vertical CCD Clock - Phase 1 Vertical CCD Clock - Phase 2 Guard Ring Output Gate

1, 13, 14, 15, 26 2 3 4 5 6 7, 8, 9, 12

Vsub Vout Vdd Vrd

1
2 3 4 5 6 7 8 9 10 11 12 13

Pin 1

26 Vsub
Pixel 1,1

25 Vog 24 Vguard 23 V1 22 V1 21 V2 20 V2 19 V2 18 V2 17 V1 16 V1 15 Vsub 14 Vsub

R
Vss N/C N/C N/C

H1 H2
N/C Vsub

Figure 3 - Package Pin Designations
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Performance Specification

KAF-6303E

3.1

Absolute Maximum Ratings
Description Symbol Vdiode Vgate1 Vgate2 Vg-g Iout Cload T RH Min. 0 -16 0 Max. 20 16 16 16 -10 15 70 90 Units V V V V mA pF o C % Notes 1, 2 1, 3 1, 4 5 6 6 7

Diode Pin Voltages Gate Pin Voltages - Type 1 Gate Pin Voltages - Type 2 Inter-Gate Voltages Output Bias Current Output Load Capacitance Storage Temperature Humidity
Notes: 1. 2. 3. 4. 5. 6. 7.

0 5

Referenced to pin Vsub. Includes pins: Vrd, Vdd, Vss, Vout, Vguard. Includes pins: V1, V2, H1, H2. Includes pins: R, Vog. Voltage difference between overlapping gates. Includes: V1 to V2, H1 to H2, V2 to H1, H2 to Vog. Avoid shorting output pins to ground or any low impedance source during operation. T=25°C. Excessive humidity will degrade MTTF.

CAUTION:

This device contains limited protection against Electrostatic Discharge (ESD). Devices should be handled in accordance with strict ESD procedures for Class 0 devices (JESD22 Human Body Model) or Class A (Machine Model). Refer to Application Note MTD/PS-0224, "Electrostatic Discharge Control"

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Performance Specification

KAF-6303E

3.2

DC Operating Conditions
Description Symbol Vrd Vss Vdd Vsub Vog Vguard Iout Min. 10.5 1.5 14.5 0 3.75 8.0 Nom. 11 2.0 15 0 4.0 10.0 -5 Max. 11.5 2.5 15.5 0 5.0 12.0 -10 Units V V V V V V mA Max DC Current (mA) 0.01 0.45 Iout 0.01 0.01 0.01 Notes

Reset Drain Output Amplifier Return Output Amplifier Supply Substrate Output Gate Guard Ring Video Output Current

1

Notes: 1. An output load sink must be applied to Vout to activate output amplifier - see Figure below.

+15V 0.1uF
~5ma

Vout 140

2N3904 or equivalent Buffered Output 1k

Figure 4 - Recommended Output Structure Load Diagram

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Performance Specification

KAF-6303E

3.3

AC Operating Condition
Description Symbol V1 V2 H1 H2 R Level Low High Low High Low High Low High Low High Min. -10.5 0.5 -10.5 0.5 -6.0 4.0 -6.0 4.0 -4.0 3.5 Nom. -10.0 1.0 -10.0 1.0 -3.0 7.0 -3.0 7.0 -3.0 4.0 Max. -9.5 1.5 -9.5 1.5 -3.0 7.0 -3.0 7.0 -2.0 5.0 Units V V V V V V V V V V Effective Capacitance 82 nF (all V1 pins) 820 nF (all V2 pins) 400 pF 400 pF 10pF Notes

Vertical CCD Clock - Phase 1 Vertical CCD Clock - Phase 2 Horizontal CCD Clock - Phase 1 Horizontal CCD Clock - Phase 2 Reset Clock

Notes: 1. All pins draw less than 10uA DC current. 2. Capacitance values relative to VSUB.

3.4

AC Timing Conditions

Description H1, H2 Clock Frequency V1, V2 Clock Frequency Pixel Period (1 Count) H1, H2 Setup Time V1, V2 Clock Pulse Width Reset Clock Pulse Width Readout Time Integration Time Line Time

Symbol f f
H V

Min.

Nom. 4 25 250 1 20 20 1719 836

Max. 15 50

Units MHz kHz ns us us ns ms us

Notes 1, 2, 3 1, 2, 3

te tHS tV tR treadout tint tline

67 0.5 10 10 531 258.2

2 4 5 6 7

Notes: 1. 50% duty cycle values. 2. CTE may degrade above the nominal frequency. 3. Rise and fall times (10/90% levels) should be limited to 5-10% of clock period. Cross-over of register clocks should be between 40-60% of amplitude. 4. R should be clocked continuously. 5. 6. 7.

treadout = ( 2056 * tline )
Integration time is user specified. Longer integration times will degrade noise performance.

tline = ( 3* tV ) + tHS + ( 3100 * te ) + te

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Performance Specification
Frame Timing
tint

KAF-6303E
tReadout 1 Frame = 2056 Lines



V1 V2 H1 H2



Line

1

2

2055

2056





Line Timing Detail
1 line V1 t V V2 H1 tHS te t V

Pixel Timing Detail
t R R

H1 te H2 Vpix
3100 counts

1 count

H2 Vout Vsat Vdark

R

Vodc Vsub

Line Content
1-10 11-16 16 - 3088 3089-3098 3099-3100

Vsat Vdark Vpix Vodc Vsub

Saturated pixel video output signal Video output signal in no light situation, not zero due to Jdark Pixel video output signal level, more electrons =more negative* Video level offset with respect to vsub Analog Ground

Photoactive Pixels Dark Reference Pixels

Dummy Pixels

* See Image Aquisition section (page 4)

Figure 5 - Timing Diagrams

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Performance Specification

KAF-6303E

4.1

Performance Specifications

All values measured at 25°C, and nominal operating conditions. These parameters exclude defective pixels.

Description
Saturation Signal Vertical CCD capacity Horizontal CCD capacity Output Node capacity Red Quantum Efficiency (=650nm) Green Quantum Efficiency (=550nm) Blue Quantum Efficiency (=450nm) Photoresponse Non-Linearity Photoresponse Non-Uniformity Dark Signal Dark Signal Doubling Temperature Dark Signal Non-Uniformity Dynamic Range Charge Transfer Efficiency Output Amplifier DC Offset Output Amplifier Bandwidth Output Amplifier Sensitivity Output Amplifier output Impedance Noise Floor Notes:
1.

Symbol

Min.

Nom.

Max.

Units

Notes

Nsat

85000 170000 190000

100000 200000 220000

120000 240000 240000

electrons / pixel 1 % % % % % electrons / pixel / sec pA/cm2
o

Rr Rg Rb PRNL PRNU Jdark

52 42 32

65 52 40
1 1 15 3.5

75 62 48
2 3 50 10 7.5 50

2 3 4

5 DSNU DR CTE Vodc f-3dB Vout/Ne~ Zout ne~ 70 0.99997 9.5 9 175

6.3 15 74 0.99999 10.5 45 10 200 15

C
5 6 7 8

electrons / pixel / sec dB V Mhz uV/e~ Ohms electrons

11.5 11 250 20

9

2. 3. 4. 5. 6. 7. 8. 9.

For pixel binning applications, electron capacity up to 330000 can be achieved with modified CCD inputs. Each sensor may have to be optimized individually for these applications. Some performance parameters may be compromised to achieve the largest signals. Worst case deviation from straight line fit, between 1% and 90% of Vsat. One Sigma deviation of a 128x128 sample when CCD illuminated uniformly. Average of all pixels with no illumination at 25oC. Average dark signal of any of 12 x 8 blocks within the sensor. (each block is 128 x 128 pixels) 20log (Nsat / ne~) at nominal operating frequency and 25oC. Video level offset with respect to ground Last output amplifier stage only. Assumes 10pF off-chip load.. Output noise at 25oC, nominal operating frequency, and tint = 0.

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Performance Specification

KAF-6303E

4.2

Typical Performance Characteristics

Spe ctral Re s pons e
0. 7

0. 6

0. 5

Quantum Efficiency

0. 4

0. 3

0. 2

0. 1

0 40 0 5 00 60 0 7 00 800 900 10 00 1100

Wave le ngth (nm)

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KAF-6303E

4.3

Cosmetic Classification
Defect tests performed at T=25oC Class Point Defects Total 35 90 Zone A 14 45 Cluster Defects Total 5 36 Zone A 2 18 Maximum Cluster Size 2 5 Column Defects Total 0 0 Zone A 0 0

C1 C2

1,2048 1024,1536 2048,1536

3072,2048

Zone A Center 1024 x 1024 Pixels

1024,512 1,1

2048,512 3072,1

Point Defect

Dark: A pixel which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation, OR Bright: A Pixel with dark current > 10,000 e/pixel/sec at 25°C. Cluster Defect A grouping of not more than "Maximum Cluster Size" defects Column Defect A grouping of >5 contiguous point defects along a single column, OR A column containing a pixel with dark current > 30,000e/pixel/sec, OR A column that does not meet the CTE specification for all exposures less than the specified Max sat. signal level and greater than 2 Ke, OR A pixel which loses more than 250 e under 2Ke illumination. Neighboring pixels The surrounding 128 x 128 pixels or ±64 columns/rows. Defect Separation Column and cluster defects are separated by no less than two (2) pixels in any direction (excluding single pixel defects). Defect Region Exclusion Defect region excludes the outer two (2) rows and columns at each side/end of the sensor.

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KAF-6303E

5.1

Quality Assurance and Reliability

Quality Strategy: All image sensors will conform to the specifications stated in this document. This will be accomplished through a combination of statistical process control and inspection at key points of the production process. Typical specification limits are not guaranteed but provided as a design target. For further information refer to ISS Application Note MTD/PS-0292, Quality and Reliability. Replacement: All devices are warranted against failure in accordance with the terms of Terms of Sale. This does not include failure due to mechanical and electrical causes defined as the liability of the customer below. Liability of the Supplier: A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Liability of the Customer: Damage from mechanical (scratches or breakage), electrostatic discharge (ESD) damage, or other electrical misuse of the device beyond the stated absolute maximum ratings, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. Cleanliness: Devices are shipped free of mobile contamination inside the package cavity. Immovable particles and scratches that are within the imager pixel area and the corresponding cover glass region directly above the pixel sites are also not allowed. The cover glass is highly susceptible to particles and other contamination. Touching the cover glass must be avoided. See ISS Application Note MTD/PS-0237, Cover Glass Cleaning for Image Sensors, for further information. ESD Precautions: Devices are shipped in static-safe containers and should only be handled at static-safe workstations. See ISS Application Note MTD/PS-0224, Electrostatic Discharge Control, for handling recommendations. Reliability: Information concerning the quality assurance and reliability testing procedures and results are available from the Image Sensor Solutions and can be supplied upon request. For further information refer to ISS Application Note MTD/PS0292, Quality and Reliability. Test Data Retention: Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. Mechanical: The device assembly drawing is provided as a reference. The device will conform to the published package tolerances.

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KAF-6303E

5.2

Ordering Information
Address all inquiries and purchase orders to: Image Sensor Solutions Eastman Kodak Company Rochester, New York 14650-2010 Phone: (585) 722-4385 Fax: (585) 477-4947 Web: www.kodak.com/go/imagers E-mail: ccd@kodak.com Eastman Kodak reserves the right to change any information contained herein without notice. All information furnished by Eastman Kodak is believed to be accurate.

WARNING:

LIFE SUPPORT APPLICATIONS POLICY

Kodak image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of the Eastman Kodak Company. Product warranty is limited to replacement of defective components and does not cover injury or property or other consequential damages.

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KAF-6303E

Revision Changes
Revision Number 0 1 2 Description of Changes Original formal version. Added UV Enhancement class (Section 4.3). Removed Appendix 1 Available Part Numbers. Added Revision Changes. Revised Class 1 cosmetic specification. (Page 13) Removed UV Enhanced device. (Page 13) Revised ESD classification to Class 0 HBM. This is not a change to the device, simply defining more accurately using updated classifications. (Page 7) Section 4.3 Cosmetic Specification: Remove Class 3, Revise Class 2 as follows: Point Defects: Total 90, Zone A 45 Clusters: Total 36, Zone A 18 Columns Total 0 Section 5.1, Quality and Reliability, updated. Section 3.3 AC Operating Conditions: Change Horizontal CCD Clock voltages for Phase 1 and Phase 2 as follow: Low Nominal from ­4.0 to ­3.0V Low Max. from ­3.5 to ­3.0V High Nominal from 6.0 to 7.0V High Max. from 6.5 to 7.0V Corrected V1, V2 Clock Capacitance from 820 to 82nF Updated ESD Caution.

3.0

3.1

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