Äîêóìåíò âçÿò èç êýøà ïîèñêîâîé ìàøèíû. Àäðåñ îðèãèíàëüíîãî äîêóìåíòà : http://vega.inp.nsk.su/~inest/YankeeRobotics/KAF-16803.pdf Äàòà èçìåíåíèÿ: Fri Oct 27 19:43:32 2006 Äàòà èíäåêñèðîâàíèÿ: Mon Oct 1 20:07:15 2012 Êîäèðîâêà: Ïîèñêîâûå ñëîâà: horizon

PRELIMINARY DEVICE PERFORMANCE SPECIFICATION Revision 0.4 July 21, 2006

KODAK KAF-16803 IMAGE SENSOR
4096 (H) X 4096 (V) FULL-FRAME CCD IMAGE SENSOR ** THE OUTPUT GATE BIAS WAS CHANGED BEFORE THIS PART WAS RELEASED TO PRODUCTION. EARLY SAMPLES, SN100 THROUGH 150, USE VOG = 6.0 , WHILE LATER PARTS, BEGINNING WITH SN=151, USE VOG = 2.0 (SEE PAGE 18).


TABLE OF CONTENTS
Summary Specification ............................................................................................................................................................... 4 Description .................................................................................................................................................................................. 4 Features ...................................................................................................................................................................................... 4 Applications ................................................................................................................................................................................. 4 Ordering Information .................................................................................................................................................................. 5 Available Part Configurations ..................................................................................................................................................... 5 Device Description ...................................................................................................................................................................... 6 Architecture ................................................................................................................................................................................. 6 Dark Reference Pixels ................................................................................................................................................................ 7 Dummy Pixels.............................................................................................................................................................................. 7 Internal Test ................................................................................................................................................................................ 7 Active Buffer Pixels ..................................................................................................................................................................... 7 Image Acquisition ........................................................................................................................................................................ 7 Charge Transport ........................................................................................................................................................................ 7 Horizontal Register ..................................................................................................................................................................... 8 Output Structure ...................................................................................................................................................................... 8 Output Load ............................................................................................................................................................................. 9 Physical Description ................................................................................................................................................................. 10 Pin Description and Device Orientation.................................................................................................................................... 10 Pin Description Table ................................................................................................................................................................ 11 Performance ............................................................................................................................................................................. 12 Image Performance Operational Conditions ........................................................................................................................... 12 Image Performance Specifications .......................................................................................................................................... 12 Performance Curves ................................................................................................................................................................. 14 Angle Response ..................................................................................................................................................................... 14 Spectral Response ................................................................................................................................................................ 14 Dark Signal ............................................................................................................................................................................ 15 Noise Floor ............................................................................................................................................................................ 15 Cosmetic Specifications ............................................................................................................................................................ 16 Cosmetic Operational Conditions ......................................................................................................................................... 16 Operation ................................................................................................................................................................................... 17 Absolute Maximum Ratings ...................................................................................................................................................... 17 Power-up Sequence .................................................................................................................................................................. 17 DC Bias Operating Conditions .................................................................................................................................................. 18 AC Operating Conditions ........................................................................................................................................................... 18 Clock Levels ........................................................................................................................................................................... 18 Timing Requirements ............................................................................................................................................................ 19 Timing Characteristics .......................................................................................................................................................... 19 Frame Timing ........................................................................................................................................................................ 20 Frame Timing Detail .............................................................................................................................................................. 20 Line Timing ............................................................................................................................................................................ 21 Pixel Timing Detail................................................................................................................................................................. 21 Timing Edge Alignment ......................................................................................................................................................... 23 Example waveforms .................................................................................................................................................................. 24 Storage and Handling ............................................................................................................................................................... 26 Storage Conditions .................................................................................................................................................................... 26 ESD ............................................................................................................................................................................................ 26 Cover Glass Care and Cleanliness ........................................................................................................................................... 26

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Soldering Recommendations ................................................................................................................................................... Mechanical Drawings ................................................................................................................................................................ Package ..................................................................................................................................................................................... Quality Assurance And Reliability ............................................................................................................................................. Quality Strategy ..................................................................................................................................................................... Replacement .......................................................................................................................................................................... Liability of the Supplier ......................................................................................................................................................... Liability of the Customer ....................................................................................................................................................... ESD Precautions .................................................................................................................................................................... Reliability ............................................................................................................................................................................... Test Data Retention ............................................................................................................................................................... Mechanical ............................................................................................................................................................................. Warning Life Support Applications Policy................................................................................................................................. Revision Changes ......................................................................................................................................................................

26 27 27 29 29 29 29 29 29 29 29 29 30 30

TABLE OF FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1 - Block Diagram ............................................................................................................................................................... 6 2 - Output Architecture (Left or Right) ............................................................................................................................... 8 3 - Recommended Output Structure Load Diagram. ........................................................................................................ 9 4 - Frame Timing ............................................................................................................................................................... 20 5 - Frame Timing Detail .................................................................................................................................................... 20 6 - Line Timing................................................................................................................................................................... 21 7 ­ Pixel Timing ................................................................................................................................................................. 21 8 - Pixel Timing Detail ....................................................................................................................................................... 22 9 - Timing Edge Alignment ............................................................................................................................................... 23 10 ­ Completed Assembly Drawing .................................................................................................................................. 27

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SUMMARY SPECIFICATION KODAK KAF-16803 IMAGE SENSOR 4096 (H) X 4096 (V) FULL FRAME CCD IMAGE SENSOR DESCRIPTION
The KAF-16803 image sensor is a redesigned version of the popular KAF-16801E image sensor (4096 x 4096 pixel resolution) with enhancements that specifically target the needs of high performance digital radiography applications. Improvements include enhanced quantum efficiency for improved DQE at higher spatial frequencies, lower noise for improved contrast in areas of high density, and anti-blooming protection to prevent image bleed from over exposure in regions outside the patient. Utilizing Kodak's proprietary single gate ITO process and micro-lens technology, the KAF16803 image sensor with its large imaging area and small pixel size provides the sensitivity, resolution and contrast necessary for high quality digital radiographs. To simplify device integration, the KAF16803 image sensor uses the same pin-out and package as the KAF-16801E image sensor.

Parameter
Architecture Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Chip Size Aspect Ratio Saturation Signal Charge to Voltage Conversion Quantum Efficiency (550nm)) Responsivity (550 nm) Read Noise (f=4 MHz) Dark Signal (T=25°C) Dark Current Doubling Temperature Linear Dynamic Range (f=4 MHz, T=25 C) Blooming Protection (4ms exposure time) Maximum Data Rate All parameters above are specified at T

Typical Value
Full Frame CCD; with Square Pixels 4145 (H) x 4128 (V) = 17.1 Mp 4127 (H) x 4128 (V) = 17 Mp 4096(H) x 4096 (V) = 16.8 Mp 9 µm (H) x 9 µm (V) 38.6 mm (H) x 37.76mm (V) square 85 K e22 µV/e60% 1302 ke/µJ/cm2 28.7 V/µJ/cm2 9 e3 e/pix/sec 6.6° C 76 dB > 100X saturation exposure 10 MHz = 25 ° C

FEATURES
· · · · · High Resolution Large Image Area High Quantum Efficiency Low Noise Architecture Broad Dynamic Range

APPLICATIONS
· · · Digital radiography Astronomy Life Sciences

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ORDERING INFORMATION AVAILABLE PART CONFIGURATIONS
The Marking Code on the back of each part is the same for all ordering options, consisting of the text `KAF-16803-ABA' followed by the serial number of the part. Available Part Numbers
KAF-16803-ABA-DD-AA KAF-16803-ABA-DD-AE KAF-16803-ABA-DP-AA KAF-16803-ABA-DP-AE

Description
Monochrome, Microlens, CERDIP Package (sidebrazed, CuW), AR coated 2 sides, Standard grade Monochrome, Microlens, CERDIP Package (sidebrazed, CuW), AR coated 2 sides, Engineering sample Monochrome, Microlens, CERDIP Package (sidebrazed, CuW), Temporaryclear coverglass, Standard grade Monochrome, Microlens, CERDIP Package (sidebrazed, CuW), Temporary clear coverglass, Engineering sample

Please contact Image Sensor Solutions for available part numbers.

KAF-16803-ABA-DD-AA Designation KAF ­ Full Frame CCD 16801 ­ 16.8 Megapixels Color A ­ Monochrome Lens B ­ Microlenses Revision A ­ Current Revision

Grade E ­ Engineering Sample A - Standard Testing A - Standard Glass D ­ Clear, AR Coated 2 Sided P ­ Temporary clear coverglass

Package D ­ Cerdip, Sidebrazed CuW) ,

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DEVICE DESCRIPTION ARCHITECTURE
V1 V2

1 Test R

1

9

KAF-16803 4 1 3 20 1
LOD

4096H x 4096V 9um x 9um Pixels

191 8

OG RD RG VDD VOUT VSS SUB H1 H2

1 20 Dark 1 6 4 1 3 20 4098 91 2

Figure 1 - Block Diagram

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DARK REFERENCE PIXELS
Surrounding the periphery of the device is a border of light shielded pixels creating a dark region. Within this dark region, exist light shielded pixels that include 20 leading dark pixels on every line. There are also 20 full dark lines at the start and 9 full dark lines at the end of every frame. Under normal circumstances, these pixels do not respond to light and may be used as a dark reference.

IMAGE ACQUISITION
An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the device. These photoninduced electrons are collected locally by the formation of potential wells at each pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel's capacity is reached, excess electrons are discharged into the lateral overflow drain to prevent crosstalk or `blooming'. During the integration period, the V1 and V2 register clocks are held at a constant (low) level.

DUMMY PIXELS
Within each horizontal shift register there are 11 leading pixels. These are designated as dummy pixels and should not be used to determine a dark reference level.

CHARGE TRANSPORT
The integrated charge from each pixel is transported to the output using a two-step process. Each line (row) of charge is first transported from the vertical CCDs to a horizontal CCD register using the V1 and V2 register clocks. The horizontal CCD is presented a new line on the falling edge of V2 while H1 is held high. The horizontal CCDs then transport each line, pixel by pixel, to the output structure by alternately clocking the H1 and H2 pins in a complementary fashion.

INTERNAL TEST
There are some pixels within each line that may not represent dark signal or the signal in the dummy pixels. These are introduced into the design to facilitate production testing. These behave differently than the buffer and dark pixels and should not be used to establish a dark reference.

ACTIVE BUFFER PIXELS
There is 1 photoactive buffer row and column adjacent to the valid photoactive pixels. These may have signals levels different from those in the imaging array and are not counted in the active pixel count.

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HORIZONTAL REGISTER
Output Structure
H2

H1

HCCD Charge Transfer

VDD

OG RG RD

Floating Diffusion

VOUT

VSS

Source Follower #1

Source Follower #2

Source Follower #3

Figure 2 - Output Architecture

The output consists of a floating diffusion capacitance connected to a three-stage source follower. Charge presented to the floating diffusion (FD) is converted into a voltage and is current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the FD. Once the signal has been sampled by the system

electronics, the reset gate (RG) is clocked to remove the signal and FD is reset to the potential applied by reset drain (RD). Increased signal at the floating diffusion reduces the voltage seen at the output pin. To activate the output structure, an off-chip current source must be added to the VOUT pin of the device. See Figure 3.

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Output Load
VDD = +15 V

Iout = 5 mA
0.1 µF VOUT

2N3904 or Equiv.

140 Ohms

1k Ohms

Buffered Video Output

Figure 3 - Recommended Output Structure Load Diagram. Note: Component values may be revised based on operating conditions and other design considerations.

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PHYSICAL DESCRIPTION PIN DESCRIPTION AND DEVICE ORIENTATION

SUB V2 V2 V1 V1 LOD N/C N/C SUB* SUB* SUB OG VDD VOUT VSS RD RG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pixel (1,1) (4096,4096)

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

V2 V2 V1 V1 SUB N/C N/C N/C N/C SUB* N/C N/C N/C N/C H2 H1 SUB

Note: Pins with the same name are to be tied together on the circuit board and have the same timing.

Notes: * Unlike the KAF-16801E, pins 9, 10, and, 25 are internally connected to SUB. They may be connected to SUB on the printed circuit board or must be left floating

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PIN DESCRIPTION TABLE
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Notes: Unlike the KAF-16801E, pins 9, 10, and, 25 are internally connected to SUB. They may be connected to SUB on the printed circuit board or must be left floating Name SUB V2 V2 V1 V1 LOD N/C N/C SUB* SUB* SUB OG VDD VOUT VSS RD RG SUB H1 H2 N/C N/C N/C N/C SUB* N/C N/C N/C N/C SUB V1 V1 V2 V2 Description Substrate Vertical CCD Clock-Phase 2 Vertical CCD Clock-Phase 2 Vertical CCD Clock-Phase 1 Vertical CCD Clock-Phase 1 Anti Blooming Drain No Connection No Connection Substrate or No Connection Substrate or No Connection Substrate Output Gate Output Amplifier Supply Video Output: Output Amplifier Return Reset Drain Reset Gate Substrate Horizontal Phase 1 Horizontal Phase 2 No Connection No Connection No Connection No Connection Substrate or No Connection No Connection No Connection No Connection No Connection Substrate Vertical CCD Clock-Phase 1 Vertical CCD Clock-Phase 1 Vertical CCD Clock-Phase 2 Vertical CCD Clock-Phase 2

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PERFORMANCE IMAGE PERFORMANCE OPERATIONAL CONDITIONS
Description
Frame time (tread
ou t

Condition - Unless otherwise noted
+ tint) variable 4 MHz 25°C integrate ­ readout cycle Nominal operating voltages and timing with min. vertical pulse width tVw = 20 µs

Notes
Includes overclock pixels

Integration time (tint) Horizontal clock frequency Temperature Mode Operation

Room temperature

IMAGE PERFORMANCE SPECIFICATIONS
Description
Saturation Signal Quantum Efficiency 550 nm

Symbol
Ne Rg PRNL PRNU Vdark,int Vdark,read DSNU T NR DR X_ab Vout/Ne Vodc f-3
dB sat

Min.

Nom.
85k 60 1 1 3 0.6 45

Max.

Units
e
-

Notes
1 2 3 4

Sample Plan
die design

%QE % % 15 3 225 e/pix/sec pA/cm2 electrons e/pix/sec

Photoresponse Non-Linearity Photoresponse Non-Uniformity Integration Dark Signal Readout Dark Current Dark Signal Non-Uniformity Dark Signal Doubling Temperature Read Noise Linear Dynamic Range Blooming Protection Output Amplifier Sensitivity DC Offset, output amplifier Output Amplifier Bandwidth Output Impedance, Amplifier

die

5

die design

6.3 9 76 100 22 Vrd ­ 3.0 100 160

°C e- rms dB x Esat µV/e V MHz Ohms 9 6 7 8

die design design

die design die

ROUT

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Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Increasing output load currents to improve bandwidth will decrease these values.
Worst case deviation from straight line fit, between 1% and 90% of Vsatmin.

One Sigma deviation of a 128x128 sample when CCD illuminated uniformly. Average of all pixels with no illumination at 25 oC.
Average dark signal of any of 32 x 32 blocks within the sensor. (each block is 128 x 128 pixels)

Output amplifier noise at 25 °C ,operating at pixel frequency up to 4MHz, bandwidth <10MHz , tint = 0, and no dark current shot noise. 20log(Vsat/VN) X_ab is the number of times above the Vsat illumination level that the sensor will bloom by spot size doubling. The spot size is 10% of the imager height. X_ab is measured at 4ms. Video level offset with respect to ground.

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PERFORMANCE CURVES
Angle Response

KAF -16803 Ang le Re spo nse
1.1 1 Normalized Angle Response 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40
De gr e e s

Ho rizontal Ve rti cal

Spectral Response

KAF-16803-ABA Spectral Response
1 0.9 0.8 0.7 0.6

QE

0.5 0.4 0.3 0.2 0.1 0 300

400

500

600

700

800

900

1000

1100

Wav e le ngth (nm)
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Dark Signal

KAF-16803 Dark Current
1000

100

Electrons

10 Integration Read out 0 0.1 20 40 60

1 -40 -20

0.01 Temperature (C)

Noise Floor
KAF-09000 Noise Floor
System noise = 6.9 electrons (10MHz bandwidth) 25 20 Noise (electrons) 15 10 5 0 -20 -10 0 10 Temperature (C) 20 30 40

Total Noise (Dark current, amplifier, system) CCD only (dark current, amplifier)

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COSMETIC SPECIFICATIONS
Cosmetic Operational Conditions

Column Defect

All cosmetic tests performed at T ~25 °C Points
<200

A grouping of more than 10 point defects along a single column -- OR -<10

Clusters
<20

Columns

A column containing a pixel with dark current > 15,000e/pixel/sec (bright column ) -- OR -A column that does not meet the CTE specification for all exposures less than the specified Max sat. signal level and greater than 2 Ke -- OR -A column that contains a pixel which loses more than 250 e under 2Ke illumination (trap defect) Column defects are separated by no less than 4 good columns. No multiple column defects (double or more) will be permitted. Column and cluster defects are separated by at least 4 good columns in the x direction.

Definitions Point Defects

Dark: A pixel which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation -- OR -Bright: A Pixel with dark current >3,000 e/pixel/sec at 25C
Cluster Defect

A grouping of not more than 10 adjacent point defects Cluster defects are separated by no less than 4 good pixels in any direction

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OPERATION ABSOLUTE MAXIMUM RATINGS
Description9
Diode Pin Voltages Gate Pin Voltages Adjacent Gate Voltages Output Bias Current LODT Diode Voltage Operating Temperature

Symbol
Vdiode Vgate1 V1-2 Iout VLODT TOP

Minimum
-0.5 -16 -16 -0.5 -60

Maximum
+20 +16 +16 -30 +13.0 60

Units
V V V mA V °C

Notes
1,2 1,3 4 5 1 7

Notes: 1. 2. 3. 4. 5. 6. 7. Referenced to pin VSUB Includes pins: VRD, VDD, VSS, VOUT. Includes pins: V1, V2, H1, H2, RG, VOG. Voltage difference between adjacent gates. Includes: V1 to V2; H1 to H2; H1 to VOG; and V1 to H2. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and lower load capacitance at the expense of reduced gain (sensitivity). Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or condition is exceeded, the device will be degraded and may be damaged. Noise performance will degrade at higher temperatures.

POWER-UP SEQUENCE
The sequence chosen to perform an initial power-up is not critical for device reliability. A coordinated sequence may minimize noise and the following sequence is recommended: 1. 2. Connect the ground pins (VSUB). Supply the appropriate biases and clocks to the remaining pins.

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DC BIAS OPERATING CONDITIONS
Description
Reset Drain Output Amplifier Return Output Amplifier Supply Substrate Output Gate (SN100 ­ 150) Output Gate (SN151 and greater) Lateral Overflow Drain Video Output Current

Symbol
VRD VVSS VVDD VSUB VOG VOG VLO
D

Minimum

Nominal
13 2.0 15.0 0 6.0** 2.0** 8.0 -5

Maximum

Units
V V V V V V V mA

Maximum DC Current (mA)
IRD = 0.01 ISS = 3.0 IOUT + ISS 0.01 0.01 0.01 0.01

Notes

IOUT

1

** The output gate bias was changed before this part was released to production. Early samples, SN100 through 150, use VOG = 6.0 , while later parts, beginning with SN=151, use VOG = 2.0 Notes: 1. An output load sink must be applied to VOUT to activate output amplifier ­ see Figure 3.

AC OPERATING CONDITIONS
Clock Levels Description
V1 Low Level V1 High Level V2 Low Level V2 High Level H1 Low Level H1 High Level H2 Low Level H2 High Level RG Low Level RG High Level

Symbol
V1L V1H V2L V2H H1L H1H H2L H2H VRGL VRGH

Level
Low High Low High Low High Low High Low High

Minimum

Nominal
-9.0 2.5 -9.0 2.5 -3.0 7.0 -3.0 7.0 6.0 11.0

Maximum

Units
V V V V V V V V V V

Effective Capacitance
250 nF

Notes
1 1

250 nF

1 1

500 pF

1 1

300 pF

1 1

13 pF

1 1

Notes: 1. All pins draw less than 10 µA DC current. Capacitance values relative to SUB (substrate).

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Timing Requirements Description
H1, H2 Clock Frequency H1, H2 Rise, Fall Times V1, V2 Rise, Fall Times V1 - V2 Cross-over H1 - H2 Cross-over H1, H2 Setup Time RG Clock Pulse Width V1, V2 Clock Pulse Width

Symbol
fH t t V V
H1r V1r

Minimum
5 5 -1

Nominal
4

Maximum
10

Units
MHz % %

Notes
1 3 3

,t ,t

H1f V1f

VCR HCR

0

1 0

V V µs ns 4

tHS tRGw tVw

5 5 20

10

20

µs

Timing Characteristics Description
Pixel Period (1 Count) Integration Time Line Time Readout Time

Symbol
te tint tlin tre
e

Minimum

Nominal
250 1.08 4,450

Maximum

Units
ns

Notes
2 5

ms ms

6 7

adout

Notes: 1. 2. 3. 4. 5. 6. 7. 50% duty cycle values. CTE will degrade above the maximum frequency. Relative to the pulse width (based on 50% of high/low levels). RG should be clocked continuously. Integration time is user specified. ( 4145 * te ) + tHS + (2 * tVw) = 1.08 msec treadout = tline * 4128 lines.

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8. Frame Timing

Frame Timing
1 Frame = 4128Lines
t V2 V1 H2 H1
Figure 4 - Frame Timing
int

t
1 2

readout

Line

3

4127

4128

Frame Timing Detail

90%

V1
10%

t
tV1r

Vw

tV1

f

90%

V2
10% tV2r tV2
f

Figure 5 - Frame Timing Detail

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Line Timing

Line Timing Detail
t
line

Line Content
4096 Active Pixels/Line 36 37 - 4132 4133 4134 - 4142 4143 - 4145

V2 V1 tV

tV t

16-35 HS

te
4145

12-15 1 - 11 Internal Test Pixels Dummy Pi xels Dark Reference Pixels*

H2
H1 RG

H1 / H2 count values

Active Buffer Pixels Photoactive Pixels **

Figure 6 - Line Timing

Pixel Timing Detail

Pixel Timing Detail
t RG H1,H1L H2 t VOUTX X=L or R
RV Vdark+Voft RG

t

e

1 Count

tHV
Vodc

VVRG VRG

VVSUB VSUB
Vsat

Figure 7 ­ Pixel Timing

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90 %

RG
RG

RG

amp

t

RGw

10 %
low

t

RGr

t

RGf

90 %

H1, H2
H1low, H2low

50 %

H1amp, H2am

p

10 %

te
2

t

H12r

tH12f

90 %

H1L
H1L

50 %

H1L

amp

10 %
low

t

e

2

tH1

Lr

tH1Lf

Figure 8 - Pixel Timing Detail

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Timing Edge Alignment

H1

VHCR

V1

V2
VVCR

V1,V2

Figure 9 - Timing Edge Alignment

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EXAMPLE WAVEFORMS

Horizontal CCD clocks

Video Waveform ­ at the CCD output and bandwidth limited at the analog to digital converter.

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Video waveform and clamp clock

Video waveform and sample clock

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STORAGE AND HANDLING STORAGE CONDITIONS
Description
Storage Temperature

COVER GLASS CARE AND CLEANLINESS
1. Maximum
70

Symbol
T
ST

Minimum
-20

Units
°C

Notes
1

The cover glass is highly susceptible to particles and other contamination. Perform all assembly operations in a clean environment. Touching the cover glass must be avoided.

2.

Note: 1. Long-term storage toward the maximum temperature will accelerate color filter degradation

Caution: Improper cleaning of the cover glass may damage these devices. Refer to Application Note MTD/PS-0237, "Cover Glass Cleaning Procedure for Image Sensors"

ESD
This device contains limited protection against Electrostatic Discharge (ESD) and is rated as a Class 0 device, JESD22 Human Body, and Class A, JESD22 Machine Mode Devices should be handled in accordance with strict handling precautions. See ISS Application Note MTD/PS0224, "Electrostatic Discharge Control".

SOLDERING RECOMMENDATIONS
Partial Heating Method: 280 °C maximum pin temperature; 10 seconds maximum duration per pin.

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MECHANICAL DRAWINGS PACKAGE

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