Äîêóìåíò âçÿò èç êýøà ïîèñêîâîé ìàøèíû. Àäðåñ îðèãèíàëüíîãî äîêóìåíòà : http://zebu.uoregon.edu/~uochep/talks/talks07/readout.pdf Äàòà èçìåíåíèÿ: Fri Jun 29 01:20:37 2007 Äàòà èíäåêñèðîâàíèÿ: Tue Oct 2 10:39:20 2012 Êîäèðîâêà: Ïîèñêîâûå ñëîâà: arp 220

SiD KPiX Electronics
David Strom ­ University of Oregon

· · · ·

Electronics requirements KPiX concept Performance Plans

Si-W work ­ p ersonnel and resp onsibilities Y. Karyotakis V. Radeka B. Holbro ok R. Lander M. Tripathi J. Brau R. Frey D. Strom M. Breidenbach, D. Freytag, N. Graf G. Haller, R. Herbst T. Nelson SLAC Electronics Mechanics Simulation

Annecy Mechanics

BNL Electronics

UC-Davis Bump Bonding Cabling Mechanics 1

Oregon Si Detectors Mechanics Simulation

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31 May 2007 ­ David Strom ­ UO


Bunch Structure at the ILC
~3000 bunches (1ms) ~200 ms

Buffer Data

Readout

· Duty cycle of bunches is low, 1/200 Only provide high current to front end during bunch train Reduces p ower · In the high granular SiD concept, o ccupancy is low Buffer data during the bunch train Minimizes digital interference to analog signals
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How many buffers are needed? Study with Luminosity = 3 â 1034, 2820 bunches/train

The following pro cesses were simulated: · · · · · e+e- hadrons e+e- e+e- µ+µ-e+e- e+e- e+e-e+e- Bhabhas Radiative bhabhas

showed that with 4 buffers, we have less than 1% dead time, everywhere in the ECAL (down to = 120 mrad). HCAL o ccupancy should b e lower.


Ron Cassel, SiD LCWS mini-workshop 17 March 2005. 3
31 May 2007 ­ David Strom ­ UO

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Dynamic range · Electromagnetic Calorimeter (300 µm silicon sensors) ­ smallest signals 1MIP ( 1MIP = 24, 000 electrons = 3.8 fC) ­ largest signals 2000 MIPs (8.0 pC) · GEM based HCAL ­ typical signals 5 to 30 fC (dep ends on gain used) · RPCs ­ typical signals 0.2 to 10pC avalanche mo de ( more than 100 pC for streamers, dep ending on gas) Design electronics for 0.3 fC to 10 pC Difficult to achieve this dynamic range in a low voltage CMOS pro cess: Max signal 1.0 V implies noise of 30 µV ?

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31 May 2007 ­ David Strom ­ UO


Power requirement ­ Can we get the heat out? Back of the envelop e calculation of temp erature in ECAL
temperature deg. C 20 18 2.5 mm of W 100mW 16 1.0 mm of Cu 100mW 14 1.0 mm of Cu + 2.5 mm of W at 100mW 12 2.5 mm of W 40mW 10 8

Thermal Conductivity: · W alloy 120W/(K-m) · Cu 400W/(K-m) Need to reduce heat to b elow 100mW/wafer ( 1mW/cm2). · HCAL will b e easier lower channel density thicker absorb er Present design 20 mW Consistent with prototyp e measurements
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6 4 2 0

0

20

40

60

80

100

120 140 Length (cm)

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31 May 2007 ­ David Strom ­ UO


KPiX Concept ­ saves up to 4 samples from each train
Bunch Clock/ ADC Counter 13 Reset Inhibit Store 4 x 13 bit memory

Cb Cs

Shaper 1

+ T1 + T2 + T3 -

Range Select

4 x 1 bit memory

C ~ 50pF d + Bias Shaper 2

Buffers + T4 4 x 13 bit memory

· · · ·

Threshold T1 is used to inhibit resets Threshold T2 is used to enable data storage Bunch clo ck (time) is stored in SRAM Analog charge is stored on capacitors
6

(set (set (13 (13

at at bit bit

2 â noise) 4 â noise) precision) precision)

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Range Switching
Bunch Clock/ ADC Counter 13 Reset Inhibit Store 4 x 13 bit memory

Cb Cs

Shaper 1

+ T1 + T2 + T3 -

Range Select

4 x 1 bit memory

C ~ 50pF d + Bias Shaper 2

Buffers + T4 4 x 13 bit memory

· Dynamic range switching (driven by threshold T3) selects Cs or Cb||Cs Feedback capacitor Cb = 10 pF stores up to 10 pC Feedback capacitor Cs = 400 fF (0.3 fC gives 0.7 mV)
N.B. Switches to capacitors closed for several RC times so signals settle
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31 May 2007 ­ David Strom ­ UO


Charge Digitization (b etween bunch crossings)
Bunch Clock/ ADC Counter 13 Reset Inhibit Store 4 x 13 bit memory

Cb Cs

Shaper 1

+ T1 + T2 + T3 -

Range Select

4 x 1 bit memory

C ~ 50pF d + Bias Shaper 2

Buffers T4 + 4 x 13 bit memory

· Time needed to discharge each capacitor stored in 13 bit memory · Time is combined with range bit to correct amplitude
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31 May 2007 ­ David Strom ­ UO


Additional features not shown in simple schematic:

· Built-in calibration system with up to 4 injections p er bunch train · Choice of two values for reset and trigger thresholds · Bias current servo system for DC coupled detectors

Additional features added in prototyp e versions 3 or 4: · · · · Polarity selection (mainly for GEMs) External trigger for test b eam Nearest neighb or trigger logic Staticly selectable feedback capacitor for tracker

All these features are tested and working
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31 May 2007 ­ David Strom ­ UO


Chip Size · Chip is implemented in TSMC 0.25µm CMOS · Single analog channels comfortably fits into 200µm by 500µm cell · Overall chip size (1024 channels) approximately: 18 mm â 6.5 mm 1.2 cm2 · Asp ect ratio helps in routing traces on silicon b oards · Could not reduce chip size without making bump b ounding more difficult Overall chip size close to optimal

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31 May 2007 ­ David Strom ­ UO


Performance ­ 64 channel prototyp e Range switching feature works as designed
KPiX4 2007_04_09_10_58_58
Output ADC

2500

2000

1500

1000

500 0 2000 4000 6000 Injected charge (fC) 8000 10000

Linear b ehavior extends to 10 pC (Nonlinear b ehavior extends range by 50% or more)
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31 May 2007 ­ David Strom ­ UO


Noise in the digitized charge value (with mo dest capacitive load)
Noise (fC) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 Channel 40 50 60

rms Fitted sigma

Different symb ols corresp ond to the four buffers on each channel

· Meets sp ec of signal noise 8:1 for MIPs in ECAL · Tracker would like signal to noise of 20:1 Performance adequate for externally triggered ECAL test b eam
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31 May 2007 ­ David Strom ­ UO


Self triggering with and without Am source (2.6 fC)
Rate
Deadtime corrected bunch occupancy
-3
2 / ndf Prob p0 34.26 / 5 2.111e-06 0.2954 ± 0.09791 0.4823 ± 0.02153

10

off source on source

p1

10-4 10-5 10
-6

2 / ndf Prob p0 p1

2.312 / 1 0.1284

-0.2056 ± 0.08493 0.6392 ± 0.02064

10-7 10-8 10
-9

10-10

2

2.5

3

3.5 4 4.5 Nominal threshold value (fC)

· Noise is Gaussian over a large range (fit to erfc) · Can easily set trigger at 1 MIP (1.9 fC) 2
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Plans · Continue testing KPiX 4 Silicon at SLAC, Oregon and GEMs at UT - Arlington)

· Submit KPiX 5 (64 or 128 channels) in early summer, main features: ­ Optimized default shaping time for trigger and reset inhibit ­ Improve biasing of MOS capacitors in threshold circuit ­ Add additional p ower bus for comparators ­ Remove some temp orary diagnostic connections Possible submission of KPiX 1024 this fall
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31 May 2007 ­ David Strom ­ UO