P R E L I M I N A R Y

SITe 512 x 512 Thermoelectrically Cooled
Scientific-Grade CCD SIA502A CCD Imager: Ideal for applications with small-area imaging and very low dark current requirements

General Description
The SIA502A CCD Imager is a silicon charge-coupled device designed to efficiently image scenes at low light levels from UV to near infrared. The sensor is fabricated as a 512 x 512 pixel, full frame area imager that utilizes a buried channel, three level polysilicon gate process. Features include a buried channel with a mini-channel for high transfer efficiency, multi-phase pinned (MPP) operation for low dark current, and a lightly doped drain (LDD) amplifier for low read noise. The device is available in a front illuminated version or a thinned, back-illuminated version that provides superior quantum efficiency.

The CCD is thermoelectrically (TE) cooled using a two stage cooler that is an integral part of the package. The sealed vacuum package prevents the device from collecting moisture when it is cooled below dew point temperature and prevents thermal conduction of heat to the device. SITe's unique thinning and back surface enhancement process provides increased blue and UV response in a flat and fully supported die.

Thermoelectric Cooler
The two stage thermoelectric cooler mounted inside the sealed vacuum package can maintain the CCD at a temperature of approximately 65 to 70 degrees C lower than the external temperature of the heat sink. The external heat sink must be properly cooled for this to be accomplished. The dark current of the CCD is a strong function of temperature. It will increase by a factor of two for every 7¼C of temperature increase. By maintaining the CCD at -35¼C, the dark current will be reduced to >200X less than its room temperature value. This is a significant reduction and worth the extra circuitry and cooling provisions needed to remove the heat from the heat sink. Since the thermoelectric cooler itself generates heat during the cooling process, the heat being removed at the heat sink is greater than the heat removed from the CCD.

Functional Description
Imaging Area
The imaging area of the SIA502A consists of 512 columns, each of which contains 512 picture elements (pixels). Each pixel measures 24µm x 24µm. The columns are isolated from each other by channel-stop regions. There is an output amplifier at each end of the two output serial registers. Only one output is used for the SIA502A. The unused upper serial register is biased off to prevent its dark current from leaking into the image array.

The signal charge collected in the imaging array is transferred along the columns, one row at a time, to the serial output register and from there to the output amplifier.

Three levels of polysilicon are used to fabricate the three gate electrodes which form the basic CCD cell (pixel). All of the pixels in a given row are defined by the same three gates. Corresponding gates in each row within a group of 512 are connected in parallel at both edges of the array. The clock signals used to drive the imaging area gates are brought in from both edges of the array, thus increasing the rate at which the rows can be shifted.

Serial Registers
The upper serial register is not used and is biased off. The charge collected in the imaging section is transferred through the transfer gate into the lower serial register phase 1 gate. The serial output register has one pixel for each column in the imaging array, plus 15 extra pixels at the end for a total of 527. The extra pixels serve as a dark reference and ensure the signal chain stabilization when the image data is received at the output.

The output of the serial register is terminated in a summing well, a DC-biased last gate (which serves to decouple the serial clock pulses from the output node), and an output amplifier. The summing well is a separately clocked gate equal in charge capacity to the other serial gates. Noiseless charge summing of consecutive serial pixels. is possible using this gate. Similarly, it is possible to sum pixels into the serial register by performing repetitive parallel transfers with the serial clocks fixed. In this manner, it is possible to collect and detect as one pixel the sum of the charge in sub-arrays of the imaging section. The sum of this sub-array charge must be less than the full well charge. The well capacity of a pixel in the serial register is greater than that of a parallel pixel to ensure that the charge handling capacity is large enough for this summing operation.

Output Structure
The imager has a single output MOSFET that is located at the end of the extended serial register. The output amplifier reset gate (RG), reset drain (RD), summing well (SW), and last gate (LG) are brought out to individual pins. This allows the operational voltages for the output to be optimized.

A positive pulse is applied to the reset gate (RG). This resets the potential of the floating diffusion to the potential connected to the reset transistor drain (RD). The reset gate voltage is then turned off and the output node (the floating diffusion) is isolated from the rest of the circuit. The charge from the serial pixel is then transferred to the output node on the falling edge of the summing well (SW) clock signal. The addition of charge on the output node causes a change in the voltage on the gate of the output MOSFET. This change in voltage is sensed at OUT.

Timing
The SITe SIA502A CCD Imager has one operating output (OUT). The device operates in the full frame mode with the entire imager's signal transferring to the one output. This timing is shown in Figure 6. The same numbered phases of the serial register are internally connected and clocked together. Likewise, all the same numbered phases of the parallel registers are internally connected and clocked together.

The transfer gate (TG) adjacent to the serial output register must be clocked. The upper transfer gate next to the unused serial register should be held low to prevent unwanted charge in this register from entering the parallel registers. The unused serial register's gates are not clocked.

During a parallel or serial shift, the signal charge is transferred one pixel at a time. A frame readout consists of at least 512 parallel shift and serial readout sequences for a full frame. A serial readout sequence consists of at least 527 serial shifts for full frame mode (15 for each serial extended region plus 512 pixels of data from the imaging array). The serials are static when the parallels are shifting and vice-versa. During integration, the serial clock is normally kept running continuously to flush the serial register and to stabilize the bias levels in the off-chip signal chain.

Multi-Phase Pinned (MPP) Operation
The multi-phase pinned (MPP) technology used on the SIA502A allows the device to be operated totally inverted during integration and line readout. The main advantage of this mode of operation is that it results in much lower dark current than conventional CCD operation. Other advantages of MPP operation are the reduction of surface residual image defect and a greater tolerance for ionizing radiation environments.

To operate the CCD in the MPP mode, the array clocks are biased sufficiently negative to invert the n-buried channel and "pin" the surface potential beneath each phase to the substrate potential. This allows holes from the p+ channel stop to populate the surface states at the silicon/silicon dioxide interface, minimizing surface dark current generation.

To enable all three phases of the array to be inverted and still retain well capacity, MPP devices have an extra implant under the phase 3 gates. During integration, this creates a potential barrier between each pixel allowing signal charge to accumulate under phases 1 and 2 at each pixel site. A consequence of this mode of operation is that the total well capacity is about 50 percent of that of a standard CCD if all the parallel clocks are operated at the same voltages. A larger well capacity can be obtained if phase 3 parallel clock high rail is operated about 3 volts higher than the phase 1 and phase 2 high rails.