Документ взят из кэша поисковой машины. Адрес оригинального документа : http://www.sao.ru/drabek/CCDP/SITe/502datsh.pdf Дата изменения: Wed Nov 11 21:49:58 1998 Дата индексирования: Tue Oct 2 01:26:19 2012 Кодировка: Поисковые слова: arp 220

SCIENTIFIC

IMAGING

TECHNOLOGIES,

INC.

512 x 512 pixel format (24µm square)
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Front-illuminated or thinned, back-illuminated versions
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Unique thinning and Quantum Efficiency enhancement processes
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Excellent QE from IR to UV
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Anti-reflection coating for visible region
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Mechanical Rigidity
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MPP technology
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Low dark current
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SITe 512 x 512 Scientific-Grade CCD
General Description The SI-502A CCD Imager is a silicon charge-coupled device designed to efficiently image scenes at low light levels from UV to near infrared. The sensor is fabricated as a 512 x 512 pixel, full frame area imager that utilizes a buried channel, three level polysilicon gate process. Features include a buried channel with a minichannel for high transfer efficiency, multi-phase pinned (MPP) operation for low dark current, and lightly doped drain (LDD) output amplifier for low read noise. The device is available in a front

Excellent charge transfer efficiency (CTE) at all signal levels
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SI-502A CCD Imager: Ideal for applications with small-area imaging requirements

On-chip output MOSFET for low noise
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Wide dynamic range
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Selectable bi-directional read-out of imaging data
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Applications include astronomy, machine vision, medical imaging, and scientific imaging

illuminated version or a thinned, back-illuminated version that provides superior quantum efficiency. SITe's unique thinning and back surface enhancement process provides increased blue and UV response in a flat and fully supported die. I t is more rugged and easier to uniformly cool than fragile edge-supported chips. The CCD imager is mounted in a non-hermetic metal package without a window.


page Functional Description Imaging Area As shown in the functional diagram, Figure 2, the imaging area of the SI-502A consists of 512 columns, each of which contains 512 picture elements (pixels). Each pixel measures 24µm x 24µm. The columns are isolated from each other by channel-stop regions. Three levels of polysilicon are used to fabricate the three gate electrodes which form the basic CCD cell (pixel). All of the pixels in a given row are defined by the same three gates. Corresponding gates in each row are connected in parallel at both edges of the array. The clock signals used to drive the imaging area gates are brought in from both edges of the array, thus increasing the rate at which the rows can be shifted. B y applying suitable voltages to the three gate phases (see timing section) potential wells are formed at each pixel site. I f an optical image is focused onto the array, an electronic analog of the scene will be collected as photoelectronic charge in the potential wells. To read out a frame, the signal charge collected in the imaging array is transferred along the columns a row at a time to one of the two serial registers and from there to an autput amplifier. Charge can be transferred to either amplifier; however, the array cannot be read out through both amplifiers simultaneously. Serial Registers The functional diagram (Figure 2) illustrates the relationship between the imaging array and the serial registers. The charge collected in the imaging section is transferred through the transfer gate into the serial register phase 1 gate. The serial register has one pixel for each column in the imaging array, plus 15 extra pixels at each end for a total of 527. The extra pixels serve as a dark reference and ensure that the signal chain is stabilized when the image data is received at the output. Each serial register is provided with an input diode and a sampling gate to allow elecrical injection of charge into the device (generally used only for testing purposes). The output of both serial registers is terminated in a summing well, a DC-biased last gate (which serves to decouple the serial clock pulses from the output node), and an output amplifier. The summing well is a separately clocked gate equal in charge capacity to the other serial

2 the sequence for moving charge packets through the serial register and parallel array. A minimum of 527 serial shifts (5I2 pixels in the image and 15 in the extended register) are required to clear the serial register after a parallel line transfer or integration period. A minimum of 512 parallel shifts are required to read out a complete image frame. The sequence for a typical full-frame readout is shown in figure 4. The parallel timing of figure 3 is for M P P operation where all of the parallel gates are held low during the integration period. When operating in the non-MPP mode, P1, P2, or both P1 and P2 are held high during integration. For full MPP operation, the parallel gates are all held low during serial readout as well as the integration period. The serial and reset gates may be clocked continuously during the integration period to drain off charge collected in the serial register. The input sample gate may be tied to the lower serial clock rail if it is not used or clocked as shown when an electrical input is required. Typical timing for the operation of an external signal clamp and sample charge detection circuit is included in the output timing diagrams for reference. Multi-Phase Pinned (MPP) Operation The multi-phase pinned (MPP) technology used on the SI-502A allows the device to be operated totally inverted during integration and line readout. The main advantage of this mode of operation is that it results in much lower dark current than conventional CCD operation. Other

gates. I t can be used to provide on-chip (noiseless) charge summing of consecutive serial pixels. Similarly, it is possible to sum pixels into the serial register by performing repetitive parallel transfers with the serial clocks fixed. In this manner, it is possible to collect and detect as one pixel the sum of the charge in sub-arrays of the imaging section, provided that the sum is less than the full well charge. The well capacity of a pixel in the serial register is greater than that of a parallel pixel to ensure that the CTE remains high. Output Structure The imager has two output MOSFETs that are located at opposite corners of the device at the ends of the extended serial registers. Figure 1 presents a schematic diagram of the output configuration. In operation, a positive pulse is applied to the reset gate (RGx). This sets the potential of the floating diffusion to the potential applied to the reset transistor drain (RDx). The reset gate voltage is then turned off and the output node (the floating diffusion) is isolated from the rest of the circuit. Charge from the serial pixel is then transferred to the output node on the falling edge of the summing well (SWx) clock signal. The addition of charge on the output node causes a change in the voltage on the gate of the output MOSFET. This change in voltage is sensed at OUTx. Timing Typical clock timing for the SITe SI-502A CCD Imager is shown in Figure 3, which gives

FIGURE 1 Output Structure


page advantages of MPP operation are the reduction of the surface residual image defect and a greater tolerance for ionizing radiation environments. To operate the CCD in the MPP mode, the array clocks are biased sufficiently negative to invert the n-buried channel and pin the surface potential beneath each phase to the substrate potential. This allows holes from the p+ channel stop to populate the surface states at the silicon/silicon dioxide interface, minimizing surface dark current generation. To enable all three phases of the array to be inverted and still retain well capacity, MPP devices have an extra implant under the phase 3 gates. During integration, this creates a potential barrier between each pixel allowing signal charge to accumulate under phases 1 and 2 at each pixel site. A consequence of this mode of operation is that the total well capacity

3 is about 50 percent of that of if all the parallel clocks are same voltages. A larger well obtained if phase 3 parallel operated about 3 volts higher and phase 2 high rails. a standard CCD operated at the capacity can be clock high rail is than the phase 1


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DEVICE SPECIFICATIONS
Measured at -45 deg. C, unless otherwise indicated, 45 kpixels/sec and standard voltages using a dual slope CDS circuit (8 µs integration time)

Minimum
Format Pixel Size Imaging Area Dark current (MPP), 20° C equivalent Readout noise Front Back Full Well signal Output gain CTE per pixel

Typical
512 x 512 pixels 24 µm x 24 µm 12.3 mm x 12.3 mm 50 pa/cm2 5 electrons 7 electrons 350,000 electrons 1.5 µV/ electron 0.99999

Maximum

70 pa/cm2 7 electrons 9 electrons

300,000 electrons 1.0 µV/ electron 0.99995

TABLE 1 Device specifications, SI-502A

DC OPERATING CONDITIONS
TERMINAL VDDx RDx LGx SUB,PKG ID GNDx OUTx ITEM OUTPUT DRAIN SUPPLY RESET DRAIN LAST GATE SUB & PACKAGE CONNECTION INPUT DIODE SUPPLY MOSFET GROUND REFERENCE MOSFET OUTPUT (LOAD) MIN 22 13 -4 5 5 STANDARD 24 15 -2 0 15 0 20 MAX 26 17 0 26 50 UNIT V V V V V V kohms

GATE TO SUBSTRATE VOLTAGES
TERMINAL RGx S#x SWx P#x P3 TGx SG ITEM RESET GATE SERIAL GATE SUMMING WELL PARALLEL GATE LOW HIGH LOW HIGH LOW HIGH LOW HIGH HIGH LOW HIGH LOW HIGH RAIL RAIL RAIL RAIL RAIL RAIL RAIL RAIL RAIL RAIL RAIL RAIL RAIL MIN -5 5 -10 5 -10 5 -10 0 0 -10 0 -10 5 STANDARD 0 12 -4 8 -4 8 -9 4 7 -9 7 -4 8 MAX 5 15 0 15 0 15 0 10 10 0 10 0 15 P TO P MAX 20 20 20 20 UNIT V V V V V V V V V V V V V

TRANSFER GATE SAMPLE GATE

20 20

TABLE 2 DC operating conditions and clock voltages, SI-502A


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FIGURE 2 SI-502A functional diagram


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FIGURE 3 SI-502A Serial and Parallel timing for both A and C outputs

FIGURE 4 SI-502A Typical full-frame readout


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FRONT PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

BACK PIN # 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13

SI-502A PIN DEFINITION
FUNCTION Substrate and Package Ground Output transistor source, a output Output Ground Reference Transfer gate, upper serial register Parallel phase 3 Parallel phase 1 Parallel phase 2 Transfer gate, lower serial register Input diode input sample gate Serial phase 1, c register Substrate and Package Ground Serial phase 2, c register *Temp. sense resistor *Temp. sense resistor Serial phase 3, c register Summing well, c output Last gate, c output Reset Gate, c output Reset Drain Supply, c output

REGISTERS a register a register a register image area image area image area c register c register c register c register

c register

c c c c c

register register register register register

Output transistor drain, c output Output transistor source, c output Output Ground Reference Transfer gate, lower serial register Parallel phase 3 Parallel phase 1 Parallel phase 2 Transfer gate, upper serial register Input diode input sample gate

c register c register c register c register image area image area image area a register a register a register

Serial phase 3, a register Serial phase 2, a register Serial phase 1, a register Summing well, a output Last gate, a output Reset transistor gate, a output Reset transistor drain, a output Output transistor drain, a output

a a a a a a a a

register register register register register register register register

SYMBOL SUB OUTa GNDa TGa P3 P1 P2 TGc IDc SGc S1c SUB N/C S2c TR1 TR2 S3c SWc LGc RGc RDc N/C N/C VDDc OUTc GNDc TGc P3 P1 P2 TGa IDa SGa N/C N/C S3a S2a S1a SWa LGa RGa RDa VDDa N/C

TABLE 3 SI-502A pin definitions


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FIGURE 5 SI-502A pin labels

FIGURE 6 SI-502A package configuration


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Quan tum Effici enc y vs. Wavele ngth (@ ro om tem p ) 100 UV AR 80 Quantum Efficiency, % Std AR

60 Fron tside 40

20

0 200 300 400 500 600 700 800 900 1000 1100 Wavel eng th , n m FIGURE 7 Typical QE curves
1E-01 1E+06

1E-02 DARK CURRENT IN ELECTRONS/PIXEL/SEC.

1E+05 DARK CURRENT IN ELECTRONS/PIXEL/SEC.

1E-03

500

100

50

10

1E+04

1E-04

1E+03

1E-05

500

100

50

10

1E+02

1E-06 24µ m pixel

1E+01

1E-07

1E+00

1E-08

1E-01

150

200
TEMPER AT UR E ( °K)

250

300

FIGURE 8 Effect of temperature on dark current. Parameter is pAmp/cm2 at 293K


SCIENTIFIC

IMAGING

TECHNOLOGIES,

INC.

Product Precautions Scientific Imaging Technologies, Inc. (SITe) realizes the use of charge-coupled devices (CCDs) for imaging is rapidly expanding into new applications. Awareness of the sensitivity of CCDs to electrostatic discharge (ESD) damage and the steps that can be implemented to prevent damage are very important to the end user. With the exception of the back-illuminated SI424A, SITe imagers do not have built-in gate protection structures. Even with the protection structures, the imagers are very sensitive to ESD damage. I t is imperative that proper precautions be taken whenever the imagers are handled. The damage caused by ESD can be immediate and fatal (hard damage) resulting in a completely nonfunctional device. ESD damage can also be more subtle with no immediate device performance degradation. In this case, the result is a slow deterioration (soft damage) that may not be apparent until after extended operation. There are three major areas where special procedures are required. We recommend that our customers use these procedures to minimize the risk of ESD damage. 1. Work areas specifically designed to minimize ESD. 2. Personnel requirements for ESD damage protection. 3. Use special ESD protected handling and shipping containers. SITe has developed a custom shipping container which grounds all the CCD pins together and allows clean and safe handling for incoming inspection and storage. For more specific information on minimizing ESD damage, refer to SITes technical briefing called Recommended ESD Handling Procedures For CCD Imagers.

SCIENTIFIC IMAGING TECHNOLOGIES, INC. P.O. Box 569 Beaverton, Oregon 97075-0569 503/644-0688 503/644-0798 fax
Scientific Imaging Technologies, Inc. (SITe) specializes in the research, design, and manufacture of charge-coupled devices (CCDs) and imaging subassemblies containing CCD components. SITes scientific grade CCDs are used in applications for astronomy, aerospace, medical, military surveillance, spectroscopy, and other areas of imaging research. Commercial uses of SITe high performance CCDs include such areas as biomedical imaging, manufacturing quality control, environmental monitoring, and nondestructive testing. With its focus on scientific-grade CCD imaging components and modules, SITe provides standard designs, user defined custom CCDs, and foundry services. SITes engineering and manufacturing team builds custom CCD imagers for use in the most demanding applications including NASA programs, satellite platforms, and other research projects. Device formats are available as front illuminated or thinned, back illuminated CCDs. Innovation, process development, and design experience date back to the founding of the group in 1974.

Information furnished by Scientific Imaging Technologies, Inc. (SITe) in this publication is believed to be accurate. Devices sold by SITe are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. SITe makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. SITe makes no warranty of merchantability or fitness for any purpose. These products are intended for use in normal commercial applications. For applications requiring extended temperature range , unusual environmental requirements, or high reliability applications , such as military, medical life support or life sustaining equipment, contact Scientific Imaging Technologies, Inc. for additional details. Copyright 1994, Scientific Imaging Technologies, Inc. All rights reserved. Printed in the U.S.A. Scientific Imaging Technologies, Inc. products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Specifications and price change privileges reserved. Scientific Imaging Technologies, Inc. and SITe are registered trademarks.

SITe Lit. No. SI-502A, version date: 12/21/95