CPSR 2
Technical guide with some observing notes can be found on the Swinburne webpages.
The page by Stuart Anderson (Caltech) http://www.ligo.caltech.edu/~anderson/instruments/pulsar/cpsr2/cpsr2.txt :
Caltech Parkes Swinburne Recorder II (CPSR2)
The basic idea is:
a) 4 RF signals downconverted to 64-128MHz using the new Parkes conversion rack.
b) ?
c) custom digitizer board--Fast Flexible Digitizer II (FFD2)
d) 2 EDT PCD-60 DMA cards
e) 30 dual-2.2GHz/1GB P4 Xeon computers with 140GB of disk space each.
f) NO TAPE DRIVES
The FFD2 is controlled over an RS-232 connection from one of the two primary nodes that have the high-speed DMA cards (arm, stop, #chans, #bits, ...). And accepts an external start signal and clock in addition to the IF signals.
The FFD2 has two halves with separate 16bit outputs: each half has 2 analog channels which can be sampled at up to 128MHz with 8bits. The resulting 4x8 bits for each half are fed into separate bit packers which each outputting 16bits to an EDT card at the appropriate rate.
As an example, the end-to-end system can operate as a dual-band 2 poln 64MHz baseband recording system, i.e., each of band A-LCP, band A-RCP, band B-LCP, and band B-RCP recorded with 2bits at 128 MHz, for a resulting 128MB/s data stream which is striped to two primary nodes, and then fed to the rest of the compute cluster over a private network.
Each bit packer is a re-programmable gate array (in-situ) which currently has been programmed to implement the following modes:
| channels | nbits |
|---|---|
| 0,2 | 4 |
| 1,2 | 4 |
| 0,3 | 4 |
| 1,3 | 4 |
| 0,1,2,3 | 2 |
The current FFD2 board has LVDS drivers which we connect directly to the EDT PCD-60 boards (nominally rated at 60MB/s but work well at much higher speeds).
The FFD2 board was designed by John Yamasaki at Caltech and the computer cluster setup and programmed by Matthew Bailes and his colleagues at Swinburne University.