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: http://www.arcetri.astro.it/irlab/instr/nics/generale/elettr.html
Дата изменения: Thu Jul 28 18:24:55 2005 Дата индексирования: Thu Jan 15 10:55:44 2009 Кодировка: |
The HAWAII detector is an array of HgCdTe photodiodes whose junction capacity collects a charge proportional to the number of photons that they receive. Each pixel is addressed by means of a multiplexer, a complex array of switches that select the desidered row and column. The voltage on the junction capacity of the selected pixel can be read in a non-destructive way or can be reset. The multiplexer is divided into four 512x512 sub-areas (quadrants), that are accessed in a parallel mode. In turn, each quadrant has a single output, used to serially read the content of single pixels. The HAWAII detector is manufactured on a best effort basis; a summary of performance specifications can be found in Table 6 . The signal level at the output correspond to about 1µ V per electron; comparing this conversion factor to the specification, is easy to understand the strict requirement on the total noise for the processing chain.
The controller is based on a set of Transputer processors, which are responsible for handling data and sending commands, and on a DSP Motorola 56001, that generates the synchronized clock pattern required to access and read the array multiplexer. The DPS can generate 24 different tables that define the clock pattern, and that transmit the reset and start-conversion commands to the selected pixel. The clock signals generated by the DPS are sent to the detector chip via a system of fast optoisolators. The electronics comprise also other boards, aimed at controlling the motors movement and acquiring service data, as temperature and pressure inside the cryostat.
The signal read on each pixels is buffered by electronics located on the same board that hosts the detector. A second amplifier is located outside the dewar; the latter also remove the voltage offset applied to the detector to avoid saturation in the next amplification stages.
The analogic-to-digital converter is based on the family of components Analogic ADC432x, that can convert at a maximum rate of 2 Mb/s. It is possible to choose different configuration of the amplification chain and different analogic converter, depending whether is preferred fast read-out time or low electronic noise. Indeed, faster acquisitions lead to higher electronic noise; this is shown in Table 7 where the noise budget is reported as a function of the sampling rate.
The read-out rate is limited by both the DPS and the analogic converter. The total conversion time is 0.3 sec, that implies a minimum integration time of 0.6 sec for a double sampling measure. The read-out rate can be as fast as 1 kHz if only a 16 16 sub-area is read. The latter might be useful to drive the tip-tilt corrector, or to observe lunar occultations.
The analogic converter boards will also host two TRAM modules, that contain a transputer T805 with a 4 Mb RAM. These transputer will temporary store the values read out of the frame and will either perform the subtraction of two consecutive frames (double sampling scheme) or coadd multiple frames (multiple sampling). Such low-level logical operations on the acquired frames are mandatory, as the time required to transmit the data to the output optical fiber link is about 1.2 seconds, too long with respect to the minimum integration time (0.6 sec).
Further details about the electronic system are given in [3].
