Äîêóìåíò âçÿò èç êýøà ïîèñêîâîé ìàøèíû. Àäðåñ îðèãèíàëüíîãî äîêóìåíòà : http://www.apo.nmsu.edu/arc35m/Instruments/ARCTIC/Development/ImagerPDR/ccd231-84-bi-nimo.pdf Äàòà èçìåíåíèÿ: Thu Dec 5 20:44:00 2013 Äàòà èíäåêñèðîâàíèÿ: Thu Feb 27 21:08:07 2014 Êîäèðîâêà: Ïîèñêîâûå ñëîâà: m 63

CCD231-84 Back Illuminated Scientific CCD Sensor 4096 x 4096 Pixels, Four Outputs Non-inverted Mode Operation
INTRODUCTION
This device extends e2v's family of scientific CCD sensors. The CCD231 has been designed to provide a large image area for demanding astronomical and scientific imaging applications. Back-illuminated spectral response combined with very low readout noise give exceptional sensitivity.

DESCRIPTION
The sensor has an image area having 4096 x 4096 pixels, split readout registers at both top and bottom with charge detection amplifiers at both ends. The pixel size is 15 m square. The image area has four separately connected sections to allow full-frame, frame transfer, split full frame or split frame-transfer modes. Depending on the mode, the readout can be through 1, 2 or 4 of the output circuits. A gate-controlled drain is also provided to allow fast dumping of unwanted data. The output amplifier is designed to give very low noise at readout rates of up to 3 MHz. The low output impedance simplifies the interface with external electronics and the optional dummy outputs are provided to facilitate common mode rejection. The package provides a compact footprint with guaranteed flatness at cryogenic temperatures. Connections are made at the top and bottom of the device via two flexi connectors that also provide a thermal break. The sides may be close butted if needed. Specifications are tested and guaranteed at 173 K (­100 °C). The CCD231 devices described here are non-inverted (nonMPP) types.

SUMMARY PERFORMANCE (Typical)
Number of pixels Pixel size Image area Outputs Package size 4096(H) x 4112(V) 15 µm square 61.4 mm x 61.4 mm 4 63.0 x 69.0 mm silicon carbide with two Package format flexi connectors Focal plane height, above base 15.0 mm Height tolerance ±10 µm Connectors two 37-way micro-D Flatness <20 µm (peak to valley) Amplifier sensitivity 7 µV/e- Readout noise Maximum pixel data rate Charge storage (pixel full well) Dark signal 5 e- at 1 MHz 2 e- at 50 kHz 3 MHz 350,000 e- 3 e-/pixel/hour (at ­100 °C)

VARIANTS
Standard silicon and deep depletion silicon device types are available with a range of AR coatings. Graded coatings and two-layer coatings are available as custom variants. Devices with other formats (e.g. 8192 x 3172 pixels) or 3side butting can also be provided in the same family. A version (CCD230) is also available with an alternative amplifier with higher charge handling capacity and higher speed (up to 5 MHz), but with slightly increased noise. An alternate ceramic/PGA package is also available. Consult e2v technologies for further information on any of the above options.

Quoted performance parameters given here are "typical" values. Specification limits are shown later in this data sheet.

Part References
CCD231-84-g-xxx g = cosmetic grade xxx = device-specific part number CCD231-84-g-141 ............. standard silicon, astro-BB CCD231-84-g-142 .... deep depletion silicon, astro-BB CCD231-84-g-E06 . deep depletion silicon, astro-ER1 CCD231-84-g-E56 ........... standard silicon, astro-mid CCD231-84-g-E57 .. deep depletion silicon, astro-mid coated coated coated coated coated

Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.
e2v technologies (uk) limited, W aterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492 e-mail: enquiries@e2v.com Internet: www.e2v.com Holding Company: e2v technologies plc e2v technologies inc. 520 W hite Plains Road, Suite 450, Tarrytown, NY10591 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148 e-mail: enquiries@e2vtechnologies.us

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PERFORMANCE (At 173 K unless stated)
Electro-Optical Specification (CCD231 Normal Mode, see note 1)
Min Peak charge storage (image) Peak charge storage (register/SW): OG low (mode 1) OG high (mode 2) Output node capacity: OG low (mode 1) OG high (mode 2) Output amplifier responsivity: mode 1 mode 2 Readout noise Maximum readout frequency Dark signal: at 173 K at 153 K Charge transfer efficiency: parallel serial Spectral range Peak quantum efficiency 275,000 5.0 99.9990 99.9990 300 Typical 350,000 300,000 350,000 200,000 600,000 7.0 2.5 2 1000 3 0.02 99.9995 99.9995 90 3 3000 2.0 100 100 1060 Max Units e /pixel e-/pixel e-/pixel e- e- V/e- V/e- e- rms kHz e-/pixel/hr e-/pixel/hr % % nm %
-

Note 2(a) 2(b)

2(c)

3 4 5 6

7

NOTES
1. Device performance will be within the limits specified by "max" and "min" when operated at the recommended voltages supplied with the test data and when measured at a register clock frequency of approximately 0.1 ­ 1.0 MHz. The noise as specified is separately measured in accordance with note 4. 2. (a) Signal level at which resolution begins to degrade. Device is non-inverted (NIMO/non-MPP), for maximum full well. (b) The summing well capacity limits the charge in the register, and its value varies with mode as shown. (c) The signal handled by the output node (for linear operation) varies with mode as shown. 3. Under normal operation (mode 1), SW is operated as a summing well or clocked as R3. OG is biased at a low DC level. Note: in this mode (with lowest read noise) the output cannot handle the full available pixel charge capacity. Alternatively (mode 2), SW may be operated as an output gate (and not therefore available for summing), biased at a low DC level, with OG raised to a high voltage (see note 9). This gives more charge-handling capacity (e.g. for higher level pixel binning). Charge transfer to the output now occurs as R2 goes low. In mode-2, the output noise will also increase by a factor of three. 4. Measured with correlated double sampling at 50 kHz nominal (mode 1). 5. Depending on the external load capacitance to be driven. The register will transfer charge at higher frequencies, but performance cannot be guaranteed. 6. Dark signal is typically measured at a device temperature of 173 K. It is a strong function of temperature and the typical average (background) dark signal at any temperature T (Kelvin) between 150 K and 300 K is given by: Qd/Qdo = 122T¨e
-6400 /T

where Qdo is the dark current at 293 K. Note that this is typical performance and some variation may be seen between devices. Dark current is lowest with the substrate voltage at +9 V, and somewhat higher with substrate at 0 V. 7. Measured with a
55

Fe X-ray source. The CTE value is quoted for the complete clock cycle (i.e. not per phase).

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SPECTRAL RESPONSE
The table below gives guaranteed minimum values of the spectral response for several variants. PRNU is also shown.
Deep depletion silicon Astro ER1 response Minimum QE (%) 20 35 65 80 45 3 3 5 Maximum Pixel Response NonUniformity PRNU (1 ) (%)

Standard silicon Astro Broadband Wavelength (nm) 350 400 500 650 900 Minimum QE (%) 40 70 80 75 25

Standard silicon Astro Midband Minimum QE (%) 20 50 80 80 25

Deep depletion silicon Astro Broadband Minimum QE (%) 40 70 75 70 40

Deep depletion silicon Astro Midband Minimum QE (%) 20 50 80 80 40

See also the figures below. Devices with an alternate spectral response may be available. Consult e2v technologies.

Typ ical QE at -100° C, Stan d ar d silico n d e v ice s
100% 90%
Q uant um Ef ficiency (%)

80% 70% 60% 50% 40% 30% 20% 10% 0% 300 400 500 60 0 700
Wave le ngt h ( nm )

800

900

1000

11 00

St andard as t ro broadband

St andard as t ro midband

T ypical QE at -100°C, De e p de ple tion de v ice s
100% 90%
Q uantum Ef ficiency ( %)

80% 70% 60% 50% 40% 30% 20% 10% 0% 300 400 500 600 700
Wave le ngt h ( nm )

800

900

1000

1100

Deep deplet ion as t ro broadband

Deep depletion as tro midband

Deep deplet ion as t ro ER1

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COSMETIC SPECIFICATIONS
Maximum allowed defect levels are indicated below. Guaranteed Specifications Grade Column defects - black or white White spots Total (black & white) spots Traps > 200e0 5 400 800 10 1 10 800 1500 15 2 15 1200 2000 20 Typical Values

0
0 <200 <400 <5

1
<3 <400 <750 <10

2
<6 <600 <1000 <15

Grades 0 and 1 are the defaults for science use. Grade 2 may have limited availability. Grade 5 devices are fully functional but with an image quality below that of grade 2, and may not meet all other specifications. Not all parameters may be tested.

DEFINITIONS
White spots A defect is counted as a white spot if the dark generation rate is 5 e-/pixel/s at 173 K. (which is also equivalent to 100 e /hour at 153 K). The temperature dependence is the same as for the mean dark signal; see note 6 above. A black spot defect is a pixel with a photo-response less than 50% of the local mean. A column is counted as a defect if it contains at least 100 white or dark single pixel defects. A trap causes charge to be temporarily held in a pixel and these are counted as defects if the quantity of trapped charge is greater than 200 eDefect measurements are excluded from the outer two rows and columns of the sensor.

Black spots Column defects Traps Defect exclusion zone

AMPLIFIER READ NOISE
The variation of typical read noise with operating frequency is shown below. (Measured using correlated double sampling with a pre-sampling bandwidth equal to twice the pixel rate in mode 1, temperature range 150 ­ 230 K).

Esti m a te d Re a d Noise (BI ) 12.0 NES elec t rons (rms ) 10.0 8.0 6.0 4.0 2.0 0.0 1. 0E+04

1. 0E+ 05

1. 0E+06

1. 0E+ 07

Frequenc y (Hz )

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DEFINITIONS
Back-Thinning
A back-thinned CCD is fabricated on the front surface of the silicon and is subsequently processed for illumination from the reverse side. This avoids loss of transmission in the electrode layer (particularly significant at shorter wavelengths or with low energy X-rays). This process requires the silicon to be reduced to a thin layer by a combination of chemical and mechanical means. The surface is "passivated" and an anti-reflection coating may be added.

Dummy Output
Each output has an associated "dummy" circuit on-chip, which is of identical design to the "real" circuit but receives no signal charge. The dummy output should have the same levels of clock feed-through, and can thus be used to suppress the similar component in the "real" signal output by means of a differential pre-amplifier. The penalty is that the noise is increased by a factor of 2. If not required the dummy outputs may be powered down.

Dark Signal
This is the output signal of the device with zero illumination. This typically consists of thermally generated electrons within the semiconductor material, which are accumulated during signal integration. Dark signal is a strong function of temperature as described in note 6.

AR Coating
Anti-reflection coatings are normally applied to the back illuminated CCD to further improve the quantum efficiency. Standard coatings optimise the response in the visible, ultra-violet or infrared regions. For X-ray detection an uncoated device may be preferable.

Correlated Double Sampling
A technique for reducing the noise associated with the charge detection process by subtracting a first output sample taken just after reset from a second sample taken with charge present.

Readout Noise
Readout noise is the random noise from the CCD output stage in the absence of signal. This noise introduces a random fluctuation in the output voltage that is superimposed on the detected signal. The method of measurement involves reverse-clocking the register and determining the standard deviation of the output fluctuations, and then converting the result to an equivalent number of electrons using the known amplifier responsivity.

Charge Transfer Efficiency
The fraction of charge stored in a CCD element that is transferred to the adjacent element by a single clock cycle. The charge not transferred remains in the original element, possibly in trapping states and may possibly be released into later elements. The value of CTE is not constant but varies with signal size, temperature and clock frequency.

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ARCHITECTURE
Chip Schematic
TOP

H3 H2 H1 DOSH OSH TGD D4 D3 D2 D1

G1 G2 G3 DOSG OSG TGD D4 D3 D2 D1

C4 C3 C2 C1

C4 C3 C2 C1

B1 B2 B3 B4

B1 B2 B3 B4

A1 A2 A3 A4 TGA OSE DOSE E3 E2 E1
E 2 V NK 2 30 S R B

A1 A2 A3 A4 TGA OSF DOSF F1 F 2 F3

BOTT OM

Image sections A and D each have a total of 4096 (H) x 1032 (V) pixels. Image sections B and C each have a total of 4096 (H) x 1024 (V) pixels. Connector-1 (and flexi) is at the "bottom" of the device (register E/F); Connector-2 is at the "top" of the device (register G/H).

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ARRANGEMENT OF ELECTRODES
Out put s H DOSH DD D DGD H1 H2 H3 H1 H2 H3 OS H TGD OGH SW H D4 D3 D2 D1 D4 D3 D2 D1 C4 C3 C2 C1 C4 C3 C2 C1 B1 B2 B3 B4 B1 B2 B3 B4 A1 A2 A3 A4 A1 A2 OGE SW E A3 TGA OS E E1 E2 E3 E1 E2 E3 E1 E2 E3 E1 E2 E3 F2 F1 F3 F2 F1 DGA DD A F3 F2 F1 F3 F2 F1 OSF SW F OGF SW G OGG H1 H2 H3 H1 H2 G3 G2 G1 G3 G2 G1 G3 G2 G1 G3 G2 G1 OSG Out put s G DOS G

DOSE Out put s E

DOS F Out put s F

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OUTPUT CIRCUIT
X designates a specific output, namely E, F, G or H. The `mapping table' on p14 shows the relationship between serial drive phases (R1, etc.) and device clock pins (X1, X2 etc)
I nt ernal connect ion to TGA or TG D

X2

X1

X3

X2

X1 SW X OGX üR X RDX

ODX

"Real" Output C OSX
n

Signal charge

Fir st stage load

External load 0V SS

Subst rat e

X2

X1 SW X OGX üR X RDX

I nt ernal connect ion to TGA or TG D

DODX

"Dumm y" O ut put C DOSX
n

Fir st stage load

External load 0V SS

Subst rat e

The first stage load of each output (real or dummy) draws a quiescent current of approximately 0.2 mA via SS. The output circuit consists of two capacitor-coupled source-follower stages. The particular design has a very high responsivity to give lowest noise. The load for the first stage is on-chip and that for the second stage is external, as next described. The DC restoration circuitry requires a pulse at the start of line readout, and this is automatically obtained by an internal connection to the adjacent transfer gate, TG. Transferring a line of charges to the register thus automatically activates the circuitry. N.B. TG pulses still need to be applied at similar intervals if only the register and/or output circuit are being operated, e.g. for test or characterisation purposes. If an output is to be powered down, it is recommended that either OD or DOD be set to SS voltage, taking care that the maximum ratings are never exceeded or that OD and DOD be disconnected. If external loads return to a voltage below SS they should also be disconnected.

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ELECTRICAL INTERFACE
CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS
Note that the hyphenated suffix symbols (e.g. R-E) indicate to which output any register or amplifier pin relates.

CONNECTOR 1
CLOCK AMPLITUDE OR DC LEVEL (V) (see note 10) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SS DOS-E OS-E OG-E DG-A R-E SW-E E1 E2 E3 ­ F3 F1 F2 SW-F R-F TG-A OG-F OS-F DOS-F SS DOD-E RD-E OD-E SS A4 A3 B4 B3 SS DD-A B1 B2 A1 A2 SS OD-F RD-F DOD-F REF DESCRIPTION Substrate (see note 12) Dummy Output Source (E) Output Source (E) Output Gate (E) (see note 9) Dump Gate (A) (see note 11) Reset Gate (E) (see note 13) Summing Well (E) (see note 9) Register Clock Phase 1 (E) Register Clock Phase 2 (E) Register Clock Phase 3 (E and F) Register Clock Phase 1 (F) Register Clock Phase 2 (F) Summing Well (F) (see note 9) Reset Gate (F) (see note 13) Transfer Gate (A) Output Gate (F) (see note 9) Output Source (F) Dummy Output Source (F) Substrate (see note 12) Dummy Output Drain (E) Reset Drain (E) Output Drain (E) Substrate (see note 12) Image Area Clock Phase 4 (A) Image Area Clock Phase 3 (A) Image Area Clock Phase 4 (B) Image Area Clock Phase 3 (B) Substrate (see note 12) Dump Drain (A) Image Area Clock Phase 1 (B) Image Area Clock Phase 2 (B) Image Area Clock Phase 1 (A) Image Area Clock Phase 2 (A) Substrate (see note 12) Output Drain (F) Reset Drain (F) Dummy Output Drain (F) 0 25 16 25 0 9 9 9 9 0 25 9 9 9 9 0 25 16 25 1 -2 9 9 9 9 9 9 9 9 9 9 1 Min 0 Typical 0 (see note 8) (see note 8) 2 0 12 10 10 10 10 10 10 10 12 10 2 (see note 8) (see note 8) 0 27.5 17 27.5 0 10 10 10 10 0 29 10 10 10 10 0 27.5 17 27.5 10 31 19 31 10 12 12 12 12 10 31 12 12 12 12 10 31 19 31 (note 9) 0.5 14 12 12 12 12 12 12 12 14 12 (note 9) Max 10 MAX RATINGS with respect to VSS (V) N/A N/A N/A ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 N/A N/A N/A -0.3 to +35 -0.3 to +25 -0.3 to +35 N/A ±20 ±20 ±20 ±20 N/A -0.3 to +35 ±20 ±20 ±20 ±20 N/A -0.3 to +35 -0.3 to +25 -0.3 to +35

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CONNECTOR 2
CLOCK AMPLITUDE OR DC LEVEL (V) (see note 10) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 REF SS DOS-G OS-G OG-G DG-D R-G SW-G G1 G2 G3 ­ H3 H1 H2 SW-H R-H TG-D OG-H OS-H DOS-H SS DOD-G RD-G OD-G SS D1 D2 C1 C2 SS DD-D C4 C3 D4 D3 SS OD-H RD-H DOD-H DESCRIPTION Substrate (see note 12) Dummy Output Source (G) Output Source (G) Output Gate (G) (see note 9) Dump Gate (D) (see note 11) Reset Gate (G) (see note 13) Summing Well (G) (see note 9) Register Clock Phase 1 (G) Register Clock Phase 2 (G) Register Clock Phase 3 (G and H) Register Clock Phase 1 (H) Register Clock Phase 2 (H) Summing Well (H) (see note 9) Reset Gate (H) (see note 13) Transfer Gate (D) Output Gate (H) (see note 9) Output Source (H) Dummy Output Source (H) Substrate (see note 12) Dummy Output Drain (G) Reset Drain (G) Output Drain (G) Substrate (see note 12) Image Area Clock Phase 1 (D) Image Area Clock Phase 2 (D) Image Area Clock Phase 1 (C) Image Area Clock Phase 2 (C) Substrate (see note 12) Dump Drain (D) Image Area Clock Phase 4 (C) Image Area Clock Phase 3 (C) Image Area Clock Phase 4 (D) Image Area Clock Phase 3 (D) Substrate (see note 12) Output Drain (H) Reset Drain (H) Dummy Output Drain (H) 0 25 16 25 0 9 9 9 9 0 25 9 9 9 9 0 25 16 25 1 -2 9 9 9 9 9 9 9 9 9 9 1 Min 0 Typical 0 (see note 8) (see note 8) 2 0 12 10 10 10 10 10 10 10 12 10 2 (see note 8) (see note 8) 0 27.5 17 27.5 0 10 10 10 10 0 29 10 10 10 10 0 27.5 17 27.5 10 31 19 31 10 12 12 12 12 10 31 12 12 12 12 10 31 19 31 (note 9) 0.5 14 12 12 12 12 12 12 12 14 12 (note 9) Max 10 MAX RATINGS with respect to VSS (V) N/A N/A N/A ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 ±20 N/A N/A N/A -0.3 to +35 -0.3 to +25 -0.3 to +35 N/A ±20 ±20 ±20 ±20 N/A -0.3 to +35 ±20 ±20 ±20 ±20 N/A -0.3 to +35 -0.3 to +25 -0.3 to +35

Note that parallel clock phase designations (sequence of phases) differ for connector-2 compared with connector-1.

NOTES
8. Do not connect to voltage supply but use a 5 mA current source or a 5 k external load. The quiescent voltage on OS is then about 6 - 8 V above the reset drain voltage and is typically 24 V. The current through these pins must not exceed 20 mA. Permanent damage may result if, in operation, OS or DOS experience short circuit conditions. For highest speed operation the output load resistor can be reduced from 5 k to approximately 2.2 k, but note that this will increase power consumption. If the device is to be operated with a register clock period of below about 1 MHz then the load may be increased to 10 k to reduce power consumption. 9. Default operation (mode 1) shown with OG set to OG-Lo, with a +2 V nominal value. In this mode SW may be clocked as R3 if a summing well function is not required. OG-Lo should have a maximum value of +5 V.

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For alternative operation in a low responsivity mode (mode 2) with increased charge handling, OG should be set to OG-Hi and SW should be operated as OG-Lo (i.e. 2V typical). See below for appropriate OG-Hi values. Charge is now read out as R2 goes low. See note 12 also for discussion about Substrate voltage (Vss). With high substrate voltage OG-Hi may be set to a nominal +20 V, which offers best linearity in mode-2. With low substrate voltage, the allowed maximum value of OG-Hi is limited to a nominal +18 V; the lower OG-Hi value has a greater non-linearity. 10. To ensure that any device can be operated the camera should be designed so that any value in the range "min" to "max" can be provided. All operating voltages are with respect to image clock low (nominally 0 V). The clock pulse low levels should be in the range 0 ± 0.5 V for image clocks. The register and SW clock low level should be +1 V higher. Reset clock low may be nominally 0 V or +1 V. In all cases, specific recommended settings will be supplied with each science-grade sensor. 11. Non-charge dumping level shown. For charge dumping, DG should be pulsed to 12 ± 2 V. 12. The substrate voltage (Vss) has a default recommended value of 0 V ("low" substrate). This is particularly recommended for deep-depletion device variants, since it optimises depletion depth for best Point Spread Function. Devices may alternatively be operated at "high" substrate, with Vss = 9 V. The high substrate setting offers slightly lower dark current, although this is usually not of primary concern when the device is cryogenically cooled. The substrate setting has some consequence for the allowed OG upper voltage level, as discussed in note 9. 13. Standard silicon variants are expected to be used with R at +10 V or more; deep depletion variants require at least +12 V. A higher value will give a correspondingly higher reset feedthrough signal in the device output (OS).

PIN CONNECTIONS (View facing pins of connector)

This numbering applies to all connectors. The connector is a Glenair 37P micro D type.

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ELECTRICAL INTERFACE CHARACTERISTICS
Electrode capacitances (defined at mid-clock level)
Typical I/I inter-phase [A, B, C and D] I/SS [A, B, C and D) Transfer gates [TGA, TGD] R total [E1, F1, G1, H1] R total [E2, F2, G2, H2] R total [E3, F3, G3, H3] 10 5 75 190 175 155 Units nF nF pF pF pF pF

The total capacitance on each phase is the sum of the inter-phase capacitance to each of the adjacent phases and the capacitance of the phase to substrate. For example, the total capacitance on phase A1 is 2 times 10 nF plus 5 nF for a total of 25 nF. The amplifier output impedance is typically 400 .

POWER UP/POWER DOWN
When powering the device up or down it for the amplifier and dump drains (pins substrate. Hence, if the substrate is to be should have a switch-on sequence which increase from zero. is critical that any specified maximum rating is not exceeded. Specifically the voltage 20, 21, 22, 29, 35, 36 and 37) must never be taken negative with respect to the operated at a positive voltage (e.g. to minimise dark current) then the drive electronics powers up all the drains to their positive voltages before the substrate voltage starts to

It is also important to ensure that excess currents (see note 8) do not flow in the OS or DOS pins. Such currents could arise from rapid charging of a signal coupling capacitor or from an incorrectly biased DC-coupled preamplifier. Similarly, for powering down, the substrate must be taken to zero voltage before the drains.

POWER CONSUMPTION
The power dissipated within the CCD is a combination of the static dissipation of the amplifiers and the dynamic dissipation from the parallel and serial clocking (i.e. driving the capacitive loads). The table below gives representative values for the components of the on-chip power dissipation for the case of continuous split-frame line-by-line readout using both registers and all the output circuits with both real and dummy amplifiers activated. The frequency is that for clocking the serial register and an appropriate value of the amplifier load is utilised in each case. Readout frequency 100 kHz 1 MHz 3 MHz Line time 21 ms 2.2 ms 800 µs Amplifier load 10 k 5 k 2.2 k Power dissipation Amplifiers 165 mW 275 mW 525 mW Serial clocks 17 mW 170 mW 510 mW Parallel clocks 3 mW 30 mW 90 mW Total 185 mW 475 mW 1,125 mW

The dissipation reduces to only that of the amplifiers during the time that charge is being collected in the image sections with both the parallel and serial clocks static.

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FRAME READOUT MODES
The device can be operated in a full-frame or split full-frame mode with readout from one, two or four amplifiers. These modes are determined by the clock pulse sequences applied to the image and register clocks. The diagrams below show some of the transfer options that are possible.

Amplifier H

Register GH Image Section D Image Section C Image Section B Image Section A Register EF

Amplifier G

Amplifier H

Register GH Image Section D Image Section C Image Section B Image Section A Register EF

Amplifier G

Amplifier E

Amplifier F

Amplifier E

Amplifier F

Full frame read-out through one amplifier

Split full frame read-out through two amplifiers

Amplifier H

Register GH Image Section D Image Section C Image Section B Image Section A Register EF

Amplifier G

Amplifier H

Register GH Image Section D Image Section C Image Section B Image Section A Register EF

Amplifier G

Amplifier E

Amplifier F

Amplifier E

Amplifier F

Split full frame read-out through four amplifiers

Split frame transfer through four amplifiers

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If the applied drive pulses are designated I1, I2, I3 and I4, then connections should be made as tabulated below to effect the following directions of transfer. I1 A section transfer towards E-F register B section transfer towards E-F register C section transfer towards G-H register D section transfer towards G-H register A section transfer towards G-H register B section transfer towards G-H register C section transfer towards E-F register D section transfer towards E-F register A1 B1 C1 D1 A4 B4 C4 D4 I2 A2 B2 C2 D2 A3 B3 C3 D3 I3 A3 B3 C3 D3 A2 B2 C2 D2 I4 A4 B4 C4 D4 A1 B1 C1 D1 TGD = "low" TGD = I1 TGA = "low" TGA = I4

The first four transfer sequences are for split frame readout. The second four are for reversing the transfer direction in either section for readout to only one of the registers. For example, using sequences 1, 2, 7 and 8 reads the whole device out through register E-F. Transfer from the image section to the register is into the phase 1 and 2 electrodes, i.e. E1, F1, G1, H1, E2, F2, G2 and H2. These electrodes must be held at clock "high" level during the process. If the register pulses are designated R1, R2 and R3, then connections should be made as tabulated below to effect the following directions of transfer. Clock Generator Drive Pulse Name E section transfer towards E output F section transfer towards F output G section transfer towards G output H section transfer towards H output E section transfer towards F output F section transfer towards E output G section transfer towards H output H section transfer towards G output R1 E2 F2 G2 H2 E1 F1 G1 H1 R2 E1 F1 G1 H1 E2 F2 G2 H2 R3 E3 F3 G3 H3 E3 F3 G3 H3

The first four sequences are for split register readout to all four outputs. The second four are for the reversal of direction in any half-section. The last electrode before the output gate is separately connected to give the function of a summing well (SW). In normal readout (i.e. if not used for summing), SW is clocked as R3. For summing, the selected SW gate is held at clock "high" level for the required number of readout cycles, and then clocked as R3 to output charge. Alternatively, SW may be operated as a second output gate to provide the option of operation in low gain/high signal mode (mode 2) with OG high. If this mode of operation is used, then the sequencing of the output clocks must be changed, as charge now transfers into the output node as R2 goes low (see notes 3 and 9). Image phases 2 and 3 should be held high during signal collection, as shown in the following figures.

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FRAME READOUT TIMING DIAGRAM
See detail of line tr ansf er

Iü1 Iü2 Iü3 Iü4

C har ge collection peri od

Rü1 Rü2 Rü3 üR

Out put Initial sweep-out Fir st valid line See det ai l of output clocking

DETAIL OF LINE TRANSFER

t

drt

t

oi

toi

t

oi

t

oi

t

oi

t

oi

t

oi

t

dtr

Iü1 Iü2 Iü3 Iü4

Rü1 Rü2 Rü3 üR

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DETAIL OF OUTPUT CLOCKING (with SW clocked as Rü3)
T
Rü1

rr

50 %

50 %

50 %

Rü2 Rü3 & SW
50 %

50 %

50 %

50 %

50 %

t
üR
50 %

dx

trx

t

wx

tfx
R eset fe edth rou gh Sign al outpu t

Output
R eset le ve l s amp ling win dow

t
90 %

rr

Sign al le ve l s amp ling win dow 50 %

10 %

t
90 %

or

Rü Edge overl aps

10 %

t

fr

LINE OUTPUT FORMAT
50 blank 2048 Active Outputs (split readout) 4096 Active Outputs (full readout) 50 blank (not required for split readout operation)

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DETAIL OF VERTICAL LINE TRANSFER (Single line dump)
Iü1 Iü2 Iü3 Iü4

tdr
Rü1 Rü2 Rü3 üR DG End of previous line r ead- out

t

tdtr tdr
g

t

drt

tdtr

t

dgr

Line transf er int o r egister

Dum p c har ge f rom register

Line transf er int o r egister

Start of next line r ead- out

CLOCK TIMING REQUIREMENTS
Symbol Ti toi tri tfi tdrt tdtr tdrg tdgr Trr trr tfr tor twx trx tfx tdx Description Line transfer Image clock Image clock Image clock Delay Delay Delay Delay Regist Regist Regist Regist Reset Reset Reset Delay time (see note 14) pulse edge overlap and transfer gate pulse rise time pulse fall time Minimum 65 7.5 1 1 5 7.5 10 7.5 300 (TBC) 10 10 0 >3 trx 10 10 10 Typical 75 10 1 1 10 10 10 10 2000 50 50 50 300 40 40 100 Maximum (see note 16) (see note 16) 0.3 toi 0.3 toi (see note 16) (see note 16) N/A N/A (see note 16) 0.05Trr 0.05Trr 0.05Trr 0.2Trr 50 50 0.05Trr Units s s s s s s s s ns ns ns ns ns ns ns ns

time, R stop to I rising time, I falling to R start time, R falling to DG rising time, DG falling to R rising er clock period (see notes 17and 18) er clock pulse rise time er clock pulse fall time er clock pulse edge overlap pulse width (see note 15) pulse rise time pulse fall time time, R falling to R falling

NOTES
14. Generally Ti = tdrt + 7toi + tdtr. 15. The R2 pulse-width is normally minimised, as shown, such that the R1 and R3 pulse widths can be increased to maximise the output reset and signal sampling intervals. 16. As set by any system specifications. 17. The typical timing is for readout at frequencies in the region of 500 kHz. 18. For highest speed operation the output load resistor can be reduced from 5 k to approximately 2.2 k, but note that this will increase power consumption. If the device is to be operated with a register clock period of below about 1 MHz, then the load may be increased to 10 k to reduce power consumption.

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PACKAGE DETAIL

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HANDLING CCD SENSORS
CCD sensors, in common with most high performance MOS IC devices, are static sensitive. In certain cases, a discharge of static electricity may destroy or irreversibly degrade the device. Accordingly, full antistatic handling precautions should be taken whenever using a CCD sensor or module. These include: · · · Working at a fully grounded workbench Operator wearing a grounded wrist strap All receiving sockets to be positively grounded

HIGH ENERGY RADIATION
Performance parameters will begin to change if the device is subject to ionising radiation. Characterisation data is held at e2v technologies with whom it is recommended that contact be made if devices are to be operated in any high radiation environment.

TEMPERATURE RANGE
Operating temperature range 153 - 323 K Storage temperature range 143 - 373 K

Evidence of incorrect handling will invalidate the warranty. All devices are provided with internal protection circuits to the gate electrodes (i.e. all CCD pins except SS, DD, RD, OD and OS) but not to the other pins. The devices are assembled in a clean room environment. e2v technologies recommend that similar precautions are taken to avoid contaminating the active surface.

Performance parameters are measured with the device at a temperature of 173 K and, as a result, full performance is only guaranteed at this nominal operating temperature. Operation or storage in humid conditions may give rise to ice on the surface when the sensor taken to low ambient temperatures, thereby causing irreversible damage. Maximum rate of heating or cooling: 5 K/min.

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